Data Conversion IC Development Tools LTC2654-L12 Demo Board - Quad SPI 12-bit

Data Conversion IC Development Tools LTC2481 16-bit, Delta-Sigma ADC (req DC

Data Conversion IC Development Tools LTC2257-12: 12-bit 40Msps ADC, CMOS Outp

Data Conversion IC Development Tools LTC1407A, 14-bit, 2-ch 3Msps SAR ADC (Un

TThe AD7172-2 is an intelligent, low noise, low power, multiplexed,Σ-Δ analog-to-digital converter (ADC) with 2- or 4-channel(fully differential/single-ended) inputs for low bandwidthsignals. The AD7172-2 has a maximum channel scan rate of6.21 kSPS (161 µs) for fully settled data. The output data ratesrange from 1.25 SPS to 31.25 kSPS.The AD7172-2 integrates key analog and digital signal conditioningblocks to allow users to configure an individual setup for eachanalog input channel in use via the SPI. Integrated true rail-to-railbuffers on the analog inputs and external reference inputs provideeasy to drive high impedance inputs. The precision 2.5 V low drift(2 ppm/°C) band gap internal reference (with an output referencebuffer) adds embedded functionality to reduce the externalcomponent count.The digital filter allows simultaneous 50 Hz and 60 Hz rejectionat a 27.27 SPS output data rate. The user can switch betweendifferent filter options according to the demands of each channel inthe application, with further digital processing functions such asoffset and gain calibration registers, which are also configurable ona per channel basis. General-purpose inputs/outputs (GPIOs)control external multiplexers synchronous to the ADC conversiontiming.The specified operating temperature range is −40°C to +105°C.The AD7172-2 is in a 24-lead TSSOP package.Applications Process control: PLC/DCS modules - Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage referenceeases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signalprocessing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimationfilters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in acommunications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoidan overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features canbe programmed using a 3-wire serial port interface (SPI).The AD9208 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. Thisproduct is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers. Fast NCO switching enabled through GPIO pins. A SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature dioide for system thermal management. 12mm × 12mm 196-Lead BGAApplications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The LTC2000A is a family of 16-/14-/11-bit 2.7Gsps current steering DACs with exceptional spectral purity.The single (1.35Gsps mode) or dual (2.7Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.35Gbps using a 675MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock.Additional features such as pattern generation, LVDS loopout and junction temperature sensing simplify system development and testing.A serial peripheral interface (SPI) port allows configuration and read back of internal registers. Operating from 1.86V and 3.3V supplies, the LTC2000A consumes 2.41W at 2.7Gsps and 1.43W at 1.35Gsps.Applications Broadband Communication Systems DOCSIS CMTS Direct RF Synthesis Radar Instrumentation Automatic Test Equipment

The LTC2358-18 is an 18-bit, low noise 8-channel simultaneous sampling successive approximation register (SAR) ADC with buffered differential, wide common mode range picoamp inputs. Operating from a 5V low voltage supply, flexible high voltage supplies, and using the internal reference and buffer, each channel of this SoftSpan™ ADC can be independently configured on a conversion-by-conversion basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to 5.12V signals. Individual channels may also be disabled to increase throughput on the remaining channels.The integrated picoamp-input analog buffers, wide input common mode range and 128dB CMRR of the LTC2358-18 allow the ADC to directly digitize a variety of signals using minimal board space and power. This input signal flexibility, combined with ±3.5LSB INL, no missing codes at 18 bits, and 96.4dB SNR, makes the LTC2358-18 an ideal choice for many high voltage applications requiring wide dynamic range.The LTC2358-18 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces. Between one and eight lanes of data output may be employed in CMOS mode, allowing the user to optimize bus width and throughput.Applications Programmable Logic Controllers Industrial Process Control Power Line Monitoring Test and Measurement

DATA CONVERSION DEVELOPMENT KITS - ADC;