14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane Noise density −152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p −154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p −154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p −155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p 1.55 W total power per channel at 2.56 GSPS (default settings) SFDR at 2.56 GSPS encode 73 dBFS at 1.8 GHz AIN at −2.0 dBFS 59 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.56 GSPS encode 59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS 53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SFDR at 2.0 GSPS encode 78 dBFS at 900 MHz AIN at −2.0 dBFS 62 dBFS at 5.53 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p SNR at 2.0 GSPS encode 62.7 dBFS at 900 MHz AIN at −2.0 dBFS 53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS full-scale voltage = 1.1 V p-p 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation Programmable FIR filters for analog channel loss equalization 2 integrated, wideband digital processors per channel 48-bit NCO Programmable decimation rates Phase coherent NCO switching Up to 4 channels available Serial port control Supports 100 MHz SPI writes and 50 MHz SPI reads Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

16-Bit, 200 kSPS, Parallel I/O A/D Converter Features: Fast 16-Bit ADC 200 kSPS Throughput Single 5 V Supply Operation Input Range: ±10 V 100 mW Max Power Dissipation Choice of External or Internal 2.5 V Reference High Speed Parallel Interface On-Chip Clock 28-Lead Skinny DIP, SSOP or SOIC Packages

Dual 12-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO Features: Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Low power, fine complex NCO allows carrier placement anywhere in DAC bandwidth while adding <300 mW power Auxiliary DACs allow I and Q gain matching and offset control Includes programmable I and Q phase compensation Internal digital upconversion capability Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed pad TQFP package

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 12-Bit DAC Features: AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL  B version: ±8 LSB INL 16-lead TSSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Micropower operation: 300 μA at 5 V (including reference current) 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V

8-Channel, 12-Bit ADC with I2C Compatible Interface in 20-Lead TSSOP Features: 12-Bit ADC with Fast Conversion Time: 2 µs Eight Single-Ended Analog Input Channels Specified for VDD of 2.7 V to 5.5 V Low Power Consumption Fast Throughput Rate: - 188 kSPS Sequencer Operation Automatic Cycle Mode I2C® Compatible Serial Interface I2C® Interface supports: Standard, Fast, and High-Speed Modes Out of Range Indicator Pin-Selectable Addressing via AS Automatic Shutdown Mode: - 1 µA max