The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS.The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.This product is protected by a U.S. patent.Applications Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipmentProduct Highlights An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding data rate clock. The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and test modes. Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth. APPLICATIONS Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers Multimode digital receivers Smart antenna systems General-purpose software radios

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and test modes. Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth. APPLICATIONS Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers Multimode digital receivers Smart antenna systems General-purpose software radios

The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing widebandsignals from dc up to 3.0 GHz. Its DAC core features a quad-switch architecture that provides exceptionally low distortion performance with an industry-leading direct RF synthesiscapability. This feature enables multicarrier generation up to the Nyquist frequency in baseband mode as well as second andthird Nyquist zones in mix mode. The output current can be programmed over the 8.66 mA to 31.66 mA range.The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies thedigital interface with existing FGPA/ASIC technology. On-chipcontrollers are used to manage external and internal clock domainvariations over temperature to ensure reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readbackof status registers.The AD9739 is manufactured on a 0.18 μm CMOS process andoperates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ballchip scale ball grid array for reduced package parasitics.Product Highlights Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix mode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. A multichip synchronization capability. Programmable differential current output with an 8.66 mA to 31.66 mA range.Applications Broadband communications systems  Military jammers Instrumentation, automatic test equipment  Radar, avionics

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC.The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.Product Highlights Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block. Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR). Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.Applications Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless

The ADAS1000 measures electrocardiac (ECG) signals, thoracic impedance, pacing artifacts,and lead-on/lead-off status and output this information in theform of a data frame supplying either lead/vector or electrodedata at programmable data rates. Its low power and small sizemake it suitable for portable, battery-powered applications.The high performance also makes it suitable for higher enddiagnostic machines. The ADAS1000 is a full-featured, 5-channel ECG includingrespiration and pace detection, while the ADAS1000-1 offersonly ECG channels with no respiration or pace features. Similarly,the ADAS1000-2 is a subset of the main device and is configuredfor gang purposes with only the ECG channels enabled (norespiration, pace, or right leg drive).The ADAS1000/ADAS1000-1/ADAS1000-2 are designed tosimplify the task of acquiring and ensuring quality ECG signals.They provide a low power, small data acquisition system forbiopotential applications. Auxiliary features that aid in betterquality ECG signal acquisition include multichannel averageddriven lead, selectable reference drive, fast overload recovery,flexible respiration circuitry returning magnitude and phaseinformation, internal pace detection algorithm operating onthree leads, and the option of ac or dc lead-off detection. Severaldigital output options ensure flexibility when monitoring andanalyzing signals. Value-added cardiac post processing isexecuted externally on a DSP, microprocessor, or FPGA.Because ECG systems span different applications, theADAS1000/ADAS1000-1/ADAS1000-2 feature a power/noisescaling architecture where the noise can be reduced at theexpense of increasing power consumption. Signal acquisitionchannels can be shut down to save power. Data rates can bereduced to save power.To ease manufacturing tests and development as well as offerholistic power-up testing, the ADAS1000/ADAS1000-1/ADAS1000-2 offer a suite of features, such as dc and ac testexcitation via the calibration DAC and cyclic redundancy check(CRC) redundancy testing, in addition to readback of allrelevant register address space.The input structure is a differential amplifier input, therebyallowing users a variety of configuration options to best suittheir application.The ADAS1000/ADAS1000-1/ADAS1000-2 are available in twopackage options, a 56-lead LFCSP package and a 64-lead LQFPpackage. Both packages are specified over a −40°C to +85°Ctemperature range. APPLICATIONSECG: Monitor & Diagnostic Bedside Patient Monitoring Portable Telemetry Holter AED Cardiac Defibrillators Ambulatory Monitors Pace Maker Programmer Patient Transport Stress testing

The AD5025 / AD5045 / AD5065 are low power, dual 12-/14-/16-bitbuffered voltage output nanoDAC® DACs offering relative accuracyspecifications of ±1 LSB INL with individual reference pins, andcan operate from a single 4.5 V to 5.5 V supply. The AD5025 /AD5045 / AD5065 also offer a differential accuracy specification of±1 LSB. The parts use a versatile 3-wire, low power Schmitttrigger serial interface that operates at clock rates up to 50 MHzand is compatible with standard SPI®, QSPI™, MICROWIRE™,and DSP interface standards. The reference for the AD5025 /AD5045 / AD5065 are supplied from an external pin and a reference buffer is provided on chip. The AD5025 / AD5045 / AD5065incorporate a power-on reset circuit that ensures the DAC outputpowers up zero scale or midscale and remains there until a validwrite takes place to the device. The AD5025 / AD5045 / AD5065contain a power-down feature that reduces the current consumptionof the device to typically 400 nA at 5 V and provides softwareselectable output loads while in power-down mode. The parts areput into power-down mode over the serial interface. Total unadjustederror for the parts is <2.5 mV. The parts exhibit very lowglitch on power-up. The outputs of all DACs can be updatedsimultaneously using the LDAC function, with the addedfunctionality of user-selectable DAC channels to simultaneouslyupdate. There is also an asynchronous CLR that clears all DACsto a software-selectable code—0 V, midscale, or full scale. Theparts also feature a power-down lockout pin, PDL, which can beused to prevent the DAC from entering power-down under anycircumstances over the serial interface.Product Highlights Dual channel available in a 14-lead TSSOP package with individual voltage reference pins. 12-/14-/16-bit accurate, ±1 LSB INL. Low glitch on power-up. High speed serial interface with clock speeds up to 50 MHz. Three power-down modes available to the user. Reset to known output voltage (zero scale or midscale). Power-down lockout capability. Applications Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

The AD5025 / AD5045 / AD5065 are low power, dual 12-/14-/16-bitbuffered voltage output nanoDAC® DACs offering relative accuracyspecifications of ±1 LSB INL with individual reference pins, andcan operate from a single 4.5 V to 5.5 V supply. The AD5025 /AD5045 / AD5065 also offer a differential accuracy specification of±1 LSB. The parts use a versatile 3-wire, low power Schmitttrigger serial interface that operates at clock rates up to 50 MHzand is compatible with standard SPI®, QSPI™, MICROWIRE™,and DSP interface standards. The reference for the AD5025 /AD5045 / AD5065 are supplied from an external pin and a reference buffer is provided on chip. The AD5025 / AD5045 / AD5065incorporate a power-on reset circuit that ensures the DAC outputpowers up zero scale or midscale and remains there until a validwrite takes place to the device. The AD5025 / AD5045 / AD5065contain a power-down feature that reduces the current consumptionof the device to typically 400 nA at 5 V and provides softwareselectable output loads while in power-down mode. The parts areput into power-down mode over the serial interface. Total unadjustederror for the parts is <2.5 mV. The parts exhibit very lowglitch on power-up. The outputs of all DACs can be updatedsimultaneously using the LDAC function, with the addedfunctionality of user-selectable DAC channels to simultaneouslyupdate. There is also an asynchronous CLR that clears all DACsto a software-selectable code—0 V, midscale, or full scale. Theparts also feature a power-down lockout pin, PDL, which can beused to prevent the DAC from entering power-down under anycircumstances over the serial interface.Product Highlights Dual channel available in a 14-lead TSSOP package with individual voltage reference pins. 12-/14-/16-bit accurate, ±1 LSB INL. Low glitch on power-up. High speed serial interface with clock speeds up to 50 MHz. Three power-down modes available to the user. Reset to known output voltage (zero scale or midscale). Power-down lockout capability. Applications Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

The AD5308 / AD5318 / AD5328 are octal 8-, 10-, and 12-bit buffered voltage output DACs in a 16-lead TSSOP. They operate from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical at 3 V. Their on-chipoutput amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308 / AD5318 / AD5328 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered, unbuffered, or VDD inputs. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA at 5 V (120 nA at 3 V). The eight channels of the DAC may be powered down individually.All three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board.APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control

The AD5308 / AD5318 / AD5328 are octal 8-, 10-, and 12-bit buffered voltage output DACs in a 16-lead TSSOP. They operate from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical at 3 V. Their on-chipoutput amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308 / AD5318 / AD5328 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered, unbuffered, or VDD inputs. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA at 5 V (120 nA at 3 V). The eight channels of the DAC may be powered down individually.All three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board.APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control