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SN65LVDS048APWRG4
|
| Price |
|
$0.87 |
$1.74 |
|
|
|
|
|
$3.26 |
|
|
| RoHS |
|
Compliant |
Yes |
Compliant |
Compliant |
Yes |
Yes |
Yes |
Yes |
Yes |
Compliant |
| Lead Status |
|
No |
Yes |
No |
No |
Yes |
Yes |
Yes |
Yes |
Yes |
No |
| Data Vin(Min)(V) |
|
3 |
|
|
3 |
|
|
|
|
|
|
| Data Input |
|
Serial |
|
|
Parallel |
|
|
|
|
|
|
| Rating |
|
Catalog |
Catalog |
|
Catalog |
|
Catalog |
|
Catalog |
Catalog |
Catalog |
| Data Transfer Rate(Typ)(MHz) |
|
30 |
|
|
1 |
|
|
|
|
|
|
| Per Channel Drive(mA) |
|
120 |
|
|
200 |
|
|
|
|
|
|
| Output Channels |
|
16 |
|
|
8 |
|
|
|
|
|
|
| Special Features |
|
Thermal Shutdown,LED Open Detection,LED Short to Ground Detection,LED Short to VLED Detection |
|
|
|
|
|
|
|
|
|
| LED Voltage(Max)(V) |
|
17 |
|
|
30 |
|
|
|
|
|
|
| Analog Dimming Steps |
|
256 |
|
|
|
|
|
|
|
|
|
| Operating Temperature Range(C) |
|
-40 to 125 |
0 to 70 |
|
-40 to 85 |
|
0 to 70 |
|
-40 to 140 |
-40 to 85,0 to 70 |
-40 to 85 |
| Ch to Ch Accuracy(Typ)(+/- %) |
|
6 |
|
|
|
|
|
|
|
|
|
| Package Size |
|
mm2 |
mm2 |
|
mm2 |
|
mm2 |
|
|
|
mm2 |
| Package Group |
|
HTSSOP,SOIC,SSOP |
PDIP,QFN,SOIC |
|
PDIP,TSSOP |
|
NFBGA |
|
SOIC,SO PowerPAD,VSON,WSON |
LQFP,LQFP,PLCC |
SOIC,TSSOP |
| Data Vin(Max)(V) |
|
5.5 |
|
|
5.5 |
|
|
|
|
|
|
| Approx. Price (US$) |
|
0.65 | 1ku |
1.16 | 1ku |
|
0.55 | 1ku |
|
9.27 | 1ku |
|
1.50 | 1ku |
4.88 | 1ku |
1.37 | 1ku |
| IEC 61000-4-2 Contact(+/- kV) |
|
|
N/A |
|
|
|
|
|
|
|
|
| Number of Nodes |
|
|
32 |
|
|
|
|
|
|
|
|
| HBM ESD(kV) |
|
|
4 |
|
|
|
|
|
|
|
|
| Duplex |
|
|
Full |
|
|
|
|
|
|
|
|
| Fail Safe |
|
|
Open |
|
|
|
|
|
|
|
|
| Fault Protection(V) |
|
|
-10 to 15 |
|
|
|
|
|
|
|
|
| Supply Voltage(s)(Nom)(V) |
|
|
5 |
|
|
|
|
|
|
|
|
| Common Mode Range |
|
|
-7 to 12 |
|
|
|
|
|
|
|
|
| Isolated |
|
|
No |
|
|
|
|
|
|
|
|
| ICC(Max)(mA) |
|
|
5 |
|
|
|
|
|
|
|
15 |
| Signaling Rate(Max)(Mbps) |
|
|
10 |
|
|
|
|
|
|
|
|
| No. of TX |
|
|
1 |
|
|
|
|
|
|
|
|
| No. of RX |
|
|
1 |
|
|
|
|
|
|
|
|
| Input VCC(Max)(V) |
|
|
|
|
|
|
|
|
17 |
|
|
| Prop Delay(ns) |
|
|
|
|
|
|
|
|
20 |
|
|
| Negative Voltage Handling at HS Pin(V) |
|
|
|
|
|
|
|
|
-12 |
|
|
| Peak Output Current(A) |
|
|
|
|
|
|
|
|
4 |
|
|
| Input VCC(Min)(V) |
|
|
|
|
|
|
|
|
8 |
|
|
| Channel Input Logic |
|
|
|
|
|
|
|
|
CMOS |
|
|
| Fall Time(ns) |
|
|
|
|
|
|
|
|
7 |
|
|
| Iq(uA) |
|
|
|
|
|
|
|
|
1 |
|
|
| Rise Time(ns) |
|
|
|
|
|
|
|
|
8 |
|
|
| Bus Voltage(V) |
|
|
|
|
|
|
|
|
110 |
|
|
| Power Switch |
|
|
|
|
|
|
|
|
MOSFET,IGBT,GaNFET |
|
|
| Number of Channels(#) |
|
|
|
|
|
|
|
|
2 |
4 |
|
| Tx FIFO Trigger Levels(#) |
|
|
|
|
|
|
|
|
|
N/A |
|
| Operating Voltage(V) |
|
|
|
|
|
|
|
|
|
3.3,5 |
|
| CPU Interface |
|
|
|
|
|
|
|
|
|
X86 |
|
| Baud Rate (max) at Vcc = 1.8V and with 16X Sampling(Mbps) |
|
|
|
|
|
|
|
|
|
N/A |
|
| Baud Rate (max) at Vcc = 5.0V and with 16X Sampling(Mbps) |
|
|
|
|
|
|
|
|
|
1 |
|
| Programmable FIFO Trigger Levels |
|
|
|
|
|
|
|
|
|
No |
|
| Baud Rate (max) at Vcc = 2.5V and with 16X Sampling(Mbps) |
|
|
|
|
|
|
|
|
|
N/A |
|
| Auto RTS/CTS |
|
|
|
|
|
|
|
|
|
Yes |
|
| FIFOs(bytes) |
|
|
|
|
|
|
|
|
|
16 |
|
| Rx FIFO Trigger Levels(#) |
|
|
|
|
|
|
|
|
|
4 |
|
| Baud Rate (max) at Vcc = 3.3V and with 16X Sampling(Mbps) |
|
|
|
|
|
|
|
|
|
1 |
|
| Input Signal |
|
|
|
|
|
|
|
|
|
|
LVDS |
| No. of Rx |
|
|
|
|
|
|
|
|
|
|
4 |
| Signaling Rate(Mbps) |
|
|
|
|
|
|
|
|
|
|
400 |
| ESD HBM(kV) |
|
|
|
|
|
|
|
|
|
|
10 |
| Function |
|
|
|
|
|
|
|
|
|
|
Receiver |
| Output Signal |
|
|
|
|
|
|
|
|
|
|
LVTTL |
