32BIT SIGMADSP AUDIO 16K/48K / REEL

32BIT SIGMADSP AUDIO 16K/48K / TRAY

32BIT SIGMADSP AUDIO 16K/48K / TRAY

13/15GHZ GAAS D/C / PCKTTAPE7 ;ROHS COMPLIANT: YES

10-BIT SD VIDEO DECODER / TRAY

Very Low Noise, Low Distortion Active RC Quad Universal Filter Features: Continuous Time—No Clock Four 2nd Order Filter Sections, 20kHz to 300kHz Center Frequency Butterworth, Chebyshev, Elliptic or Equiripple Delay Response Lowpass, Bandpass, Highpass Responses 99dB Typical S/N, ±5V Supply (Q = 1) 93dB Typical S/N, Single 5V Supply (Q = 1) Rail-to-Rail Input and Output Voltages DC Accurate to 3mV (Typ) ±0.5% Typical Center Frequency Accuracy “Zero-Power” Shutdown Mode Single or Dual Supply, 5V to 10V Total Resistor-Programmable fO, Q, Gain

A2B Main 4xPDM XCVR wI2S/TDM Features:A2B BUS FEATURES Line topology Single main node, multiple subordinate nodes Up to 15 m between nodes and up to 40 m overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency node to node communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power subordinate nodes Configurable with SigmaStudio/SigmaStudio+ graphical software tool AEC-Q100 qualified for automotive applicationsA2B TRANSCEIVER FEATURES Configurable A2B bus main node or subordinate node Programmable via I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

256 Position SPI/I2C Selectable Digital Potentiometer Features: 256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 8 μA Wide operating temperature −40°C to +125°C SDO output allows multiple device daisy-chaining Evaluation board available

SigmaDSP Compact Digital Audio Processor with Extended Internal Memory Features: Qualified for automotive applications High performance SigmaDSP core enables low latency and audio applications Active Noise Cancellation (ANC) Echo-Canceller and Noise Reduction (ECNR) Surround sound algorithms Features SigmaStudio, a proprietary graphical Integrated Development Environment (IDE), for the development of custom signal flows Comprehensive Toolbox of pre-defined building blocks Faster design time with proven solutions Intuitive system design 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 24 kWords of program memory 80 kWords of parameter/data RAM 6144 SIMD instructions per sample at 48 kHz 1600 ms digital audio delay pool at 48 kHz Audio I/O and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz Flexible configuration of I2S, left and right justified, and up to 16-channel TDM formats on serial data pins 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range Stereo S/PDIF input and output at 192 kHz Four PDM microphone input channels Multichannel, byte addressable TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor I2C and SPI control interfaces (both slave and master) Standalone operation Self-boot from serial EEPROM 6-channel, 10-bit SAR auxiliary control ADC 14 multipurpose pins for digital controls and outputs On-chip regulator for generating 1.2 V from 1.8 V to 3.3 V supply 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm exposed pad Temperature range: −40°C to +105°C

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP