DIGITAL POT 100KOHM SINGLE TSOT-8; End To End Resistance:100kohm; No. of Pots:Single; Control Interface:Up Down; Track Taper:Linear; Resistance Tolerance:± 20%; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Potentiometer IC Case Style:TSOT; No. of Pins:8Pins; No. of Steps:32; Temperature Coefficient:± 35ppm/°C; Operating Temperature Min:-40°C; Operating Temperature Max:105°C; Packaging:Each; Product Range:Single 32-Tap Volatile Digital Pots; Automotive Qualification Standard:-; MSL:MSL 1 - Unlimited; SVHC:No SVHC (20-Jun-2016)

Digital Potentiometer 50k Ohm 2 Circuit 256 Taps I2C Interface 10-MSOP

Prescaler .18GHz divide by 8 prescaler

SigmaDSP Compact Digital Audio Processor with Extended Internal Memory Features: Qualified for automotive applications High performance SigmaDSP core enables low latency and audio applications Active Noise Cancellation (ANC) Echo-Canceller and Noise Reduction (ECNR) Surround sound algorithms Features SigmaStudio, a proprietary graphical Integrated Development Environment (IDE), for the development of custom signal flows Comprehensive Toolbox of pre-defined building blocks Faster design time with proven solutions Intuitive system design 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 24 kWords of program memory 80 kWords of parameter/data RAM 6144 SIMD instructions per sample at 48 kHz 1600 ms digital audio delay pool at 48 kHz Audio I/O and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz Flexible configuration of I2S, left and right justified, and up to 16-channel TDM formats on serial data pins 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range Stereo S/PDIF input and output at 192 kHz Four PDM microphone input channels Multichannel, byte addressable TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor I2C and SPI control interfaces (both slave and master) Standalone operation Self-boot from serial EEPROM 6-channel, 10-bit SAR auxiliary control ADC 14 multipurpose pins for digital controls and outputs On-chip regulator for generating 1.2 V from 1.8 V to 3.3 V supply 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm exposed pad Temperature range: −40°C to +105°C

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP

Stereo PDM to I2S/TDM Converter Features: 2 channels of PDM audio inputs from digital microphones 64× decimation ratio of PDM to PCM audio data 24-bit resolution to support high sound pressure level (SPL) microphones 126 dB A-weighted SNR 4 kHz to 96 kHz output sampling rate Bit clock rates of 64×, 128×, 192×, 256×, 384×, or 512× the output sampling rate Automatic PDM clock generation Automatic power-down when BCLK is removed 0.36 mA DVDD operating current at 48 kHz sampling rate and 1.8 V supply Slave I2S or TDM output interface Up to TDM-16 supported Configurable TDM slots I/O supply voltage from 1.70 V to 3.63 V DVDD core supply voltage from 1.10 V to 1.98 V 4 μA typical DVDD shutdown current 9-ball, 1.26 mm × 1.26 mm, 0.4 mm pitch WLCSP Power-on reset

2, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier Features: Digital input stereo, high efficiency Class-D amplifier Operates from a single 4.5 V to 16.5 V supply State-of-the-art, proprietary, filterless - modulation 106.5 dB SNR at PO = 8.1 W, RL = 8 , AV = 19 dB, PVDD = 12 V, A weighted 0.004% THD + N at 5 W into 8 38.5 V rms output voltage noise, f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 Pop and clickless on and off sequence 2 14.67 W output at 12 V supply to 4 loads at <1% THD + N 2 14.4 W output at 16 V supply to 8 loads at <1% THD + N Mono mode for increased maximum output power 1 49.69 W output at 16 V supply to 2 loads at <1% THD + N Support for low impedance loads As low as 3 Ω/5 μH in stereo mode As low as 2 Ω/5 μH in mono mode High power efficiency 93.8% efficiency into an 8 Ω load 90.6% efficiency into a 4 Ω load 12.34 mA quiescent current with single 12 V PVDD supply Single-supply operation with internal LDOs or option to use an external 5 V and 1.8 V supply for lowest power consumption I2C control and hardware modes with up to 16 pin-selectable slots/addresses Supported sample rates from 8 kHz to 192 kHz with 24-bit resolution Multiple PCM audio serial data formats TDM slave with support for up to 16 devices on a single bus I2S or left justified slave Adjustable full-scale output tailored for many PVDD sources 2- and 3-cell Li-Ion batteries Digital volume control with selectable smooth ramp Automatic power-down function Supply monitoring automatic gain control (AGC) function reduces system brownout Standalone operational mode without I2C Temperature sensor with 1°C step readout via I2C Short-circuit, undervoltage, and thermal protection Thermal early warning Power-on reset PVDD sensing ADC 40-lead, 6 mm × 6 mm LFCSP with thermal pad

Ultra Low Power, Class-D Audio Amplifier Features: Filterless digital input, mono differential output Class-D amplifier with 3-level Σ-Δ modulation optimized for headphone drive Operates from single 1.8 V supply 80 mW output power, 16 Ω load at <0.1% THD + N 2.57 μV rms noise, 113 dB A weighted signal-to-noise ratio and dynamic range 0.003% THD + N at 30 mW, 1 kHz output 32 Ω load I2C control with up to 4 pin selectable addresses or standalone operation Multiple serial data formats TDM, I2S, or left justified slave PDM input operating from 2.8224 MHz to 12.288 MHz Support sample rates from 8 kHz to 768 kHz 3.9 μs latency with 6 MHz PDM input Flexible digital gain adjustment DC blocking high-pass filter with programmable corner frequency 1.55 mW typical idle power in high performance mode Low power modes for reduced power consumption Flexible output gain limiter and clipping Auto power-down feature with zero digital input Short-circuit protection Pop and click suppression User-selectable ultralow EMI emissions mode Power-on reset 1.8 V PVDD supply 1.2 V to 1.8 V IOVDD supply 11-ball, 0.984 mm × 1.444 mm, 0.35 mm pitch WLCSP

Up to 1 GHz Dual-SHARC+ DSP w/ Integrated Arm Cortex-A5 Features:SHARC+ Core Infrastructure 800 MHz (max) or 1 GHz (max) Core clock frequency 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedArm Core Infrastructure: 1 GHz Arm Cortex-A5 (with Neon/FPU) 32 kByte/32 kByte L1 Instr./Data Cache 256 kByte L2 CacheMemory 2048 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 8x Precision Clock Generators 2x 4-channel PDM Mic Inputs 40 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin / 6-pin 6x I2C,3x UARTs 2x Link Ports 16x General Purpose Timer, 1x General Purpose Counter 3x Watchdog Timers ePPI USB 2.0 HS OTG Controller 10/100 EMAC 10/100/1000 EMAC w/AVB and 1588 2x CAN FD 8-ch 12bit Housekeeping ADC 135 GPIO pins, 40 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball FCBGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Very Low Noise, Differential Amplifier and 5MHz Lowpass Filter Features: Programmable Differential Gain via Two External Resistors Adjustable Output Common Mode Voltage Operates and Specified with 3V, 5V, ±5V Supplies 0.5dB Ripple 4th Order Lowpass Filter with 5MHz Cutoff 82dB S/N with 3V Supply and 2VP-P Output Low Distortion, 2VP-P, 800Ω Load 1MHz: 93dBc 2nd, 96dBc 3rd Fully Differential Inputs and Outputs Compatible with Popular Differential Amplifier Pinouts Available in an SO-8 Package