DIGITAL ISOLATOR, 2CH, -40 TO 125DEG C ROHS COMPLIANT: YES

VOLTAGE DIGITAL POTENTIOMETER ROHS COMPLIANT: YES

SPECIAL FUNCTION IC ROHS COMPLIANT: YES

A2B Main 4xPDM XCVR wI2S/TDM Features:A2B BUS FEATURES Line topology Single main node, multiple subordinate nodes Up to 15 m between nodes and up to 40 m overall cable length Communication over distance Synchronous data Multichannel I2S/TDM to I2S/TDM Synchronous clock, phase aligned in all nodes Low latency node to node communication Control and status information I2C to I2C GPIO and interrupt Bus power or local power subordinate nodes Configurable with SigmaStudio/SigmaStudio+ graphical software tool AEC-Q100 qualified for automotive applicationsA2B TRANSCEIVER FEATURES Configurable A2B bus main node or subordinate node Programmable via I2C interface 8-bit to 32-bit multichannel I2S/TDM interface Programmable I2S/TDM data rate Up to 32 upstream and 32 downstream channels PDM interface Programmable PDM clock rate Up to 4 high dynamic range microphone inputs Simultaneous reception of I2S data with up to 4 PDM microphones Unique ID register for each transceiver Crossover or straight-through cabling Programmable settings to optimize EMC performance

256 Position SPI/I2C Selectable Digital Potentiometer Features: 256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 8 μA Wide operating temperature −40°C to +125°C SDO output allows multiple device daisy-chaining Evaluation board available

2, 31.76 W, Digital Input, Filterless Stereo Class D Audio Amplifier Features: Digital input stereo, high efficiency Class-D amplifier Operates from a single 4.5 V to 16.5 V supply State-of-the-art, proprietary, filterless - modulation 106.5 dB SNR at PO = 8.1 W, RL = 8 , AV = 19 dB, PVDD = 12 V, A weighted 0.004% THD + N at 5 W into 8 38.5 V rms output voltage noise, f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 Pop and clickless on and off sequence 2 14.67 W output at 12 V supply to 4 loads at <1% THD + N 2 14.4 W output at 16 V supply to 8 loads at <1% THD + N Mono mode for increased maximum output power 1 49.69 W output at 16 V supply to 2 loads at <1% THD + N Support for low impedance loads As low as 3 Ω/5 μH in stereo mode As low as 2 Ω/5 μH in mono mode High power efficiency 93.8% efficiency into an 8 Ω load 90.6% efficiency into a 4 Ω load 12.34 mA quiescent current with single 12 V PVDD supply Single-supply operation with internal LDOs or option to use an external 5 V and 1.8 V supply for lowest power consumption I2C control and hardware modes with up to 16 pin-selectable slots/addresses Supported sample rates from 8 kHz to 192 kHz with 24-bit resolution Multiple PCM audio serial data formats TDM slave with support for up to 16 devices on a single bus I2S or left justified slave Adjustable full-scale output tailored for many PVDD sources 2- and 3-cell Li-Ion batteries Digital volume control with selectable smooth ramp Automatic power-down function Supply monitoring automatic gain control (AGC) function reduces system brownout Standalone operational mode without I2C Temperature sensor with 1°C step readout via I2C Short-circuit, undervoltage, and thermal protection Thermal early warning Power-on reset PVDD sensing ADC 40-lead, 6 mm × 6 mm LFCSP with thermal pad

Ultra Low Power, Class-D Audio Amplifier Features: Filterless digital input, mono differential output Class-D amplifier with 3-level Σ-Δ modulation optimized for headphone drive Operates from single 1.8 V supply 80 mW output power, 16 Ω load at <0.1% THD + N 2.57 μV rms noise, 113 dB A weighted signal-to-noise ratio and dynamic range 0.003% THD + N at 30 mW, 1 kHz output 32 Ω load I2C control with up to 4 pin selectable addresses or standalone operation Multiple serial data formats TDM, I2S, or left justified slave PDM input operating from 2.8224 MHz to 12.288 MHz Support sample rates from 8 kHz to 768 kHz 3.9 μs latency with 6 MHz PDM input Flexible digital gain adjustment DC blocking high-pass filter with programmable corner frequency 1.55 mW typical idle power in high performance mode Low power modes for reduced power consumption Flexible output gain limiter and clipping Auto power-down feature with zero digital input Short-circuit protection Pop and click suppression User-selectable ultralow EMI emissions mode Power-on reset 1.8 V PVDD supply 1.2 V to 1.8 V IOVDD supply 11-ball, 0.984 mm × 1.444 mm, 0.35 mm pitch WLCSP

Up to 1 GHz Dual-SHARC+ DSP w/ Integrated Arm Cortex-A5 Features:SHARC+ Core Infrastructure 800 MHz (max) or 1 GHz (max) Core clock frequency 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedArm Core Infrastructure: 1 GHz Arm Cortex-A5 (with Neon/FPU) 32 kByte/32 kByte L1 Instr./Data Cache 256 kByte L2 CacheMemory 2048 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 8x Precision Clock Generators 2x 4-channel PDM Mic Inputs 40 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin / 6-pin 6x I2C,3x UARTs 2x Link Ports 16x General Purpose Timer, 1x General Purpose Counter 3x Watchdog Timers ePPI USB 2.0 HS OTG Controller 10/100 EMAC 10/100/1000 EMAC w/AVB and 1588 2x CAN FD 8-ch 12bit Housekeeping ADC 135 GPIO pins, 40 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball FCBGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Quad-Channel Digital Isolator (3/1 Channel Directionality) Features: Qualified for automotive applications Low power operation Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics High common-mode transient immunity: >25 kV/μs See data sheet for additional features

5 KV rms Isolated Precision Half-Bridge Driver, 4 A Output Features: 4 A peak output current Working voltage High-side or low-side relative to input: 537 V peak High-side to low-side differential: 800 V peak High frequency operation: 1 MHz maximum  3.3 V to 5 V CMOS input logic 4.5 V to 18 V output drive  UVLO at 2.5 V VDD1 ADuM3223A/ADuM4223A UVLO at 4.1 V VDD2 ADuM3223B/ADuM4223B UVLO at 7.0 V VDD2 ADuM3223C/ADuM4223C UVLO at 11.0 V VDD2 Precise timing characteristics  54 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching CMOS input logic levels  High common-mode transient immunity:>25 kV/μs Enhanced system-level ESD performance per IEC 61000-4-x  High junction temperature operation: 125°C  Thermal shutdown protection  Default low output Safety and regulatory approvals ADuM4223 wide-body, 16-lead SOIC UL recognition per UL 1577  5000 V rms for 1 minute SOIC long package  CSA Component Acceptance Notice 5A  VDE certificate of conformity  DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak  Qualified for automotive applications