High Performance, Polyphase Energy, and Class S Power Quality Monitoring IC Features: 7 high performance, 24-bit Σ-Δ ADCs 101 dB SNR at 8 kSPS with PGA = 1 Wide input voltage range: ±1 V, 707 mV rms full scale at gain = 1 Differential inputs ±25 ppm/°C maximum channel drift (including ADC, internal VREF, PGA drift) enabling 10000:1 dynamic input range, Class 0.2 metrology with standard external components With the optional ADSW-PQ-CLS Power Quality Library, the complete IEC 61000-4-30 Class S power quality standard is implemented including: Power frequency 10 sec average Magnitude of the supply Dips and swells Interruptions Rapid voltage change Flicker Mains signaling voltage Underdeviation and overdeviation Voltage and current Magnitude Harmonics Interharmonics Unbalance THD Waveform recording Optional ADSW-PQ-CLS Power Quality Library compatible with ARM® Cortex microcontrollers VRMS one-cycle and IRMS one-cycle refreshed each cycle VRMS and IRMS filtered and updated every sample 10 cycle rms/12 cycle rms Period registers to calculate line frequency, one per phase Zero crossing and zero-crossing timeout Phase angle measurements Supports CTs Multipoint phase and gain compensations for CTs Rogowski coils with the addition of an external analog integrator Continuous resampled data available Waveform buffer Advanced metrology feature set Total and fundamental active power, volt amperes reactive (VAR), volt amperes (VA), watthour, VAR hour, and VA hour Total and fundamental IRMS and VRMS Power factor Supports active energy standards: IEC 62053-21 and IEC 62053-22, EN50470-3, OIML R46, and ANSI C12.20 Supports reactive energy standards: IEC 62053-23 and IEC 62053-24 High speed communication port: 20 MHz SPI Integrated temperature sensor with 12-bit successive approximation register (SAR) ADC ±3°C accuracy from −40°C to +85°C

The AD6634 is a two channel (dual) digital Receive Signal Processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient-decimating filter. A 16-bit parallel output port provides a means of accommodating high data rate outputs such as in WBCDMA applications.The AD6634 is part of Analog Devices' SoftCellTM Multi-carrier transceiver chipset designed for compatibility with Analog Devices' family of high sample rate IF sampling ADCs (AD6640 / AD6644 12 & 14 bit). The SoftCellTM receiver comprises a digital receiver capable of digitizing an entire spectrum of carriers and digitally selecting the carrier of interest for tuning and channel selection. This architecture eliminates redundant radios in wireless base station applications.High dynamic range decimation filters offer a wide range of decimation rates. The RAM-based architecture allows easy reconfiguration for multi-mode applications.

Up-Down Converters I/Q Receiver SMT, 17 - 21 GHz

3kV rms, Default Low, Dual-Channel Digital Isolators (2/0 Channel Directionality) Features: Up to 100 Mbps data rate (NRZ) Low propagation delay: 23 ns typical Low dynamic power consumption Bidirectional communication 3.3 V to 5 V level translation High temperature operation: 125°C High common-mode transient immunity: >25 kV/μs Default high output: ADuM1280/ADuM1281 Default low output: ADuM1285/ADuM1286 Narrow body, RoHS-compliant, 8-lead SOIC Safety and regulatory approvals UL recognition: 3000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak Qualified for automotive applications

The LT6604-15 consists of two matched, fully differential amplifiers, each with a 4th order, 15MHz lowpass ?lter. The ?xed frequency lowpass ?lter approximates a Chebyshev response. By integrating a ?lter and a differential amplifier, distortion and noise are made exceptionally low. At unity gain, the measured in band signal-to-noise ratio is an impressive 76dB. At higher gains, the input referred noise decreases, allowing the part to process smaller input differential signals without significantly degrading the signal-to-noise ratio.Gain and phase are highly matched between the two channels. Gain for each channel is independently programmed using two external resistors. The LT6604-15 enables level shifting by providing an adjustable output common mode voltage, making it ideal for directly interfacing to ADCs.The LT6604-15 is fully specified for 3V operation. The differential design enables outstanding performance at a 2VP-P signal level for a single 3V supply. See the back page of this datasheet for a complete list of related single and dual differential amplifiers with integrated 2.5MHz to 20MHz lowpass ?lters.Applications Dual Differential ADC Driver Plus Filter Single-Ended to Differential Converter Matched, Dual, Differential Filter Stage Common Mode Translation of Differential Signals High Speed ADC Antialiasing and DAC Smoothing in Wireless Infrastructure or Networking Applications High Speed Test and Measurement Equipment Medical Imaging

SigmaDSP Digital Audio Processor Features: Qualified for automotive applications Fully programmable audio DSP for enhanced sound processing Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows Clock oscillator for generating master clock from crystal Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V Up to 6144 SIMD instructions per sample at 48 kHz Up to 40 kWords of parameter/data RAM Up to 800 ms digital audio delay pool at 48 kHz Audio input/output and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital input/output up to a sample rate of 192 kHz Flexible configuration for TDM, I2S, left and right justified formats, and PCM Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB DNR Stereo S/PDIF input and output Four PDM microphone input channels Multichannel, byte addressable, TDM serial ports Integer PLL and flexible clock generators Integrated die temperature sensor

SPECIAL FUNCTION IC;

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP

AUDIO / VIDEO ANALOG DEVELOPMENT KITS;

The AD8191 is a DVI/HDMI switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. Outputs can be set to a high impedance state to reduce the power dissipation and/or allow the construction of larger arrays using the wire-OR technique.Flexible channel bundling modes allow the AD8191 to be configured as a 4:1 single DVI/HDMI link switch, a dual 8:1 TMDS channel switch, or a single 16:1 TMDS channel switch.The AD8191 is provided in a 100-lead LQFP lead-free packagespecified to operate over the 0°C to 70°C temperature range.PRODUCT HIGHLIGHTS Supports data rates up to 1.65Gbps, enabling UXGA (1600x1200) DVI resolutions and 1080p HDMI formats. Input cable equalizer enables use of long cables at the input (more than 20 meters of 24 AWG cable at 1080p). Auxiliary switch allows routing of DDC signals for a single-chip, fully HDMI 1.2a receive-compliant solution.APPLICATIONS Multi-input displays and projectors A/V receivers Set-top boxes Advanced television (HDTV)