VOLTAGE DIGITAL POTENTIOMETER;

TEMPERATURE SENSOR;

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Dual Channel, 256-Position, SPI, Nonvolatile Digital Potentiometer Features: 10 kΩ and 100 kΩ resistance options Resistor tolerance: ±8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time <75 μs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 3 mm × 3 mm package optionQualified for automotive applications

Four-ADC, Two-DAC, Low Power Codec with Audio Processor Features: Programmable audio processing engine Fast (up to 768 kHz) and slow processing paths Biquad filters, limiters, volume controls, and mixing Low latency, 24-bit ADCs and DACs 102 dB SNR (through PGA and ADC with A weighted filter) 108 dB combined SNR (through DAC and headphone with A weighted filter) Serial port sampling rate from 8 kHz to 192 kHz 5 μs analog-to-analog latency 4 single-ended analog inputs, configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output, single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital input/output of 1.8 V to 3.3 V Digital signal processing (DSP) core of 1.1 V to 1.8 V Low power I2C and SPI control interfaces, self boot from I2C EEPROM 7 multipurpose (MPx) pins for digital controls and outputs

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Real-Time Ethernet Multiprotocol (REM) Switch Features: 144-lead CSP_BGA RoHS compliant package −40°C to +105°C industrial temperature range rating 3.3 V input/output buffers IEEE 802.3, 10 Mbps/100 Mbps, half and full duplex, IPv6 and IPv4 communication 2 independent Ethernet ports: 1 MII and 1 RMII interface per port Support for all industrial protocols PROFINET Class B and Class C with fast startup (Version 2.3) EtherNet/IP with QuickConnect, CIP Sync, and CIP Motion Modbus TCP EtherCAT Ethernet POWERLINK Host interface transfer rate: 32 bits per 28 ns Supports EtherCAT cycle times down to 12.5 μs and PROFINET cycle times down to 31.25 μs PI Net Load Class III capable DLR (supervisor and node, announce and beacon based), MRPD, HSR, PRP, shared device, controller redundancy IEEE 1588Version 2 support: ordinary clock; both peerto peer and end to end transparent clocks, raw frames, and UDP 8 independent timer signals synchronized with an internal precision timer 4 independently programmable timer signals for timer capture events or timer output events 4 timer signals create programmable periodic waveforms synchronized to the internal precision timer DCP, LLDP, DHCP, RSTP, VLAN, IGMP snooping support Forwarding table with aging and learning Drive LEDs for link activity

SPECIAL FUNCTION IC;

SPECIAL FUNCTION IC;

SPECIAL FUNCTION IC;