The AD8110 and AD8111 are high-speed 16 × 8 video crosspointswitch matrices. They offer a –3 dB signal bandwidthgreater than 260 MHz, and channel switch times of less than25 ns with 1% settling. With –78 dB of crosstalk and –97 dBisolation (@ 5 MHz), the AD8110/AD8111 are useful in manyhigh-speed applications. The differential gain and differentialphase of better than 0.02% and 0.02° respectively, along with0.1 dB flatness out to 60 MHz, make the AD8110/AD8111ideal for video signal switching.The AD8110 and AD8111 include eight independent outputbuffers that can be placed into a high impedance state for parallelingcrosspoint outputs so that off channels do not load theoutput bus. The AD8110 has a gain of +1, while the AD8111offers a gain of +2. They operate on voltage supplies of ±5 Vwhile consuming only 50 mA of idle current. The channelswitching is performed via a serial digital control (which canaccommodate “daisy chaining” of several devices) or via a parallelcontrol, allowing updating of an individual output without reprogrammingthe entire array.The AD8110/AD8111 is packaged in an 80-lead LQFP packageand is available over the extended industrial temperature rangeof –40°C to +85°C.Applications Routing of high-speed signals including: Composite video (NTSC, PAL, S, SECAM) Component video (YUV, RGB) Compressed video (MPEG, Wavelet) 3-level digital video (HDB3)

The AD8400/AD8402/AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kOhm, 10 kOhm, 50 kOhm or 100 kOhm has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.

The AD8400/AD8402/AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kOhm, 10 kOhm, 50 kOhm or 100 kOhm has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.

The AD8400/AD8402/AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kOhm, 10 kOhm, 50 kOhm or 100 kOhm has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.

The AD8400 / AD8402 / AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.

The AD9826 is a complete analog signal processor for imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC, and Programmable Gain Amplifier (PGA), multiplexed to a high-performance 16-bit A/D converter.APPLICATIONS Flatbed Document Scanners Digital Copier Multifunction Peripherals Infrared Imaging Applications Machine Vision

The AD9959 consists of four direct digital synthesizer (DDS)cores that provide independent frequency, phase, and amplitudecontrol on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such asfiltering, amplification, or PCB layout-related mismatches.Because all channels share a common system clock, they areinherently synchronized. Synchronization of multiple devices is supported.The AD9959 can perform up to a 16-level modulation of fre-quency, phase, or amplitude (FSK, PSK, ASK). Modulation isperformed by applying data to the profile pins. In addition, theAD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation. The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI-compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices, Inc., DDS products. Flexibility is provided by four data pins (SDIO_0/SDIO_1/SDIO_2/SDIO_3) that allow four programmable modes of serial I/O operation.The AD9959 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates four integrated, high speed 10-bit DACs with excellent wideband and narrow-band SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier. The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale currents for each channel. The DDS acts as a high resolution frequency divider with the REFCLK as the input and the DAC providing the output. The REFCLK input source is common to all channels and can be driven directly or used in combination with an integrated REFCLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REFCLK input also features an oscillator circuit to support an external crystal as the REFCLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REFCLK multiplier.The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9959 operates over the industrial temperature range of −40°C to +85°C.APPLICATIONSAgile local oscillators Phased array radars/sonars Instrumentation Synchronized clocking RF source for AOTF

The ADA4430-1 is a fully integrated video reconstruction filter that combines excellent video specifications with low power consumption and an ultralow power disable, making it ideal for portable video filtering applications. With 1 dB frequency flatness out to 8 MHz and 50 dB rejection at 27 MHz, the ADA4430-1 is ideal in SD video applications including NTSC and PAL.The ADA4430-1 operates on single supplies as low as 2.5 V and as high as 6 V while providing the dynamic range required by the most demanding video systems.The ADA4430-1 also provides an on-chip dc offset to avoid clipping of the sync tips at the filter output, as well as SAG correction that permits smaller capacitor values to be used in applications with ac-coupled outputs.The ADA4430-1 is available in a 6-lead SC70 package and is rated to work in the extended automotive temperature range of -40°C to +125°C.

The ADuC831 is a fully integrated 247 kSPS data acquisitionsystem incorporating a high performance self-calibrating multi-channel12-bit ADC, dual 12-bit DACs, and programmable8-bit MCU on a single chip.The microcontroller core is an 8052, and therefore 8051-instruction-set compatible with 12 core clock periods per machinecycle. 62 kBytes of nonvolatile Flash/EE program memory areprovided on-chip. Four kBytes of nonvolatile Flash/EE datamemory, 256 bytes RAM and 2 kBytes of extended RAM arealso integrated on-chip.The ADuC831 also incorporates additional analog functionalitywith two 12-bit DACs, power supply monitor, and a band gapreference. On-chip digital peripherals include two 16-bit Σ-∆DACs, dual output 16-bit PWM, watchdog timer, time intervalcounter, three timers/counters, Timer 3 for baud rate generationand serial I/O ports (I2C, SPI and UART).On-chip factory firmware supports in-circuit serial download anddebug modes (via UART), as well as single-pin emulation modevia the EA pin. The ADuC831 is supported by QuickStart™ andQuickStart Plus development systems featuring low cost softwareand hardware development tools. The part is specified for 3 V and 5 V operation over the extendedindustrial temperature range, and is available in a 52-lead plasticquad flatpack package and in a 56-lead chip scale package.Applications Optical networking—laser power control Base station systems Precision instrumentation, smart sensors Transient capture systems DAS and communications systems

The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).