Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 600 (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EPAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 600 (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EPAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

AUDIO CONTROL;

LINE INTERFACE UNIT, LQFP-100; IC Function: Line Interface Unit; Supply Voltage Min: 3.15V; Supply Voltage Max: 3.45V; IC Package Type: LQFP; No. of Pins: 100Pins; Operating Temperature Min: -40°C; Operating Temperature Max: 85°C; Product Range: -; Automotive Qualification Standard: -; RoHS Phthalates Compliant: To Be Advised; MSL: MSL 3 - 168 hours

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP

AR-EBZ"A00336"EB-O8R-1Z; Silicon Manufacturer:Analog Devices; Silicon Core Number:ADA4891-1; Kit Application Type:Amplifier; Application Sub Type:Operational Amplifier; Kit Contents:Bare Board; Product Range:-; SVHC:No SVHC (20-Jun-2016); Features:8-Lead NSOIC Package High Speed Rail-to-Rail Op Amp

4-Channel Digital Potentiometer Features: 256-Position Replaces 1,2 or 4 Potentiometers 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Available Options Power Shutdown - Less than 5 µA 3-Wire SPI-Compatible Serial Data Input 10 MHz Update Data Loading Rate 2.7 V to 5.5 V Single-Supply Operation Midscale Preset

12BIT VIDEO DECODER 7188 LQFP80; Resolution (Bits):12bit; Supply Voltage Min:3V; Supply Voltage Max:3.6V; TV / Video Case Style:LQFP; No. of Pins:80Pins; ADC Sample Rate:54MSPS; No. of Input Channels:12Channels; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Each; Product Range:-; Automotive Qualification Standard:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (20-Jun-2016); Amplifier Type:Video; Bandwidth:6MHz; Base Number:7188; IC Generic Number:7188; Input Format:Analogue; Logic Function Number:7188; No. of Amplifiers:0Amplifiers; Operating Temperature Range:-40°C to +85°C; Output Format:Digital; Power Dissipation Pd:550mW; Supply Current:105mA; Supply Voltage Range:3V to 3.6V; TV / Video Type:Decoder; Termination Type:Surface Mount Device

Low Cost, Low Power, True RMS-to-DC Converter Features: Delivers true rms or average rectified value of ac waveform Fast settling at all input levels Accuracy: ±10 μV ± 0.25% of reading (B grade) Wide dynamic input range  100 μV rms to 3 V rms (8.5 V p-p) full-scale input range  Larger inputs with external scaling Wide bandwidth: 1 MHz for −3 dB (300 mV)  65 kHz for additional 1% error Zero converter dc output offset No residual switching products Specified at 300 mV rms input  Accurate conversion with crest factors up to 10  Low power: 300 μA typical at ±2.4 V  High-Z FET separately powered input buffer RIN ≥ 1012 Ω, CIN ≤ 2 pF  Precision dc output buffer  Wide power supply voltage range Dual: ±2.4 V to ±18 V; single: 4.8 V to 36 V 4 mm × 4 mm LFCSP and 8 mm × 6 mm QSOP packages ESD protected