SRAM X18 18M 2.5V CORE ZBT SLO

SRAM 8K x 8 Dual-Port RAM

3.3V 128Kx36 ZBT Synchronous Flow-Through SRAM with 3.3V I/O

The DS2431-A1 is an AEC-Q100 Grade 1 qualified version of the DS2431. The logical behavior of both versions is identical. The DS2431-A1 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. The DS2431-A1 communicates over the single-conductor 1-Wire bus. The communication follows the standard 1-Wire protocol. Each device has its own unalterable and unique 64-bit ROM registration number that is factory lasered into the chip. The registration number is used to address the device in a multidrop 1-Wire net environment.ApplicationsAccessory/PCB IdentificationAutomotive Cable Assembly IdentificationAutomotive Sensor Identification and Calibration Data Storage

The DS28EC20 is a 20480-bit, 1-Wire® EEPROM organized as 80 memory pages of 256 bits each. An additional page is set aside for control functions. Data is written to a 32-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, blocks of eight memory pages can be write protected or put in EPROM-Emulation mode, where bits can only be changed from a 1 to a 0 state. The DS28EC20 communicates over the single-conductor 1-Wire bus. The communication follows the standard 1-Wire protocol. Each device has its own unalterable and unique 64-bit ROM registration number. The registration number is used to address the device in a multidrop 1-Wire net environment.ApplicationsCard/Module Identification in Rack-Based SystemsDevice AuthenticationIEEE 1451.4 SensorsInk and Toner Cartridge IDMedical and Industrial Sensor Identification/CalibrationPCB IdentificationSmart Cable

The DS2704 provides 1280 bits of EEPROM datastorage and a Secure Hash Algorithm (SHA) engine.The Dallas 1-Wire® interface enables serialcommunication on a single battery contact and the64-bit unique serial number allows multidropnetworking and identification of individual devices.The 1280-bit memory is organized as 5 pages of 32bytes each and supports storage of battery cellcharacteristics, charging voltage, current, andtemperature parameters, as well as battery packmanufacturing data. The EEPROM pages are incircuit rewritable and can be individually locked towrite protect data.The DS2704 employs the Secure Hash Algorithm(SHA-1) specified in the Federal Informationpublication 180-1 and 180-2, and ISO/IEC 10118-3.SHA-1 provides a robust cryptographic solution toensure battery packs or other peripherals have beenmanufactured by authorized sources. The DS2704processes a host transmitted challenge and the 64-bit secret key stored on chip to produce a 160-bitresponse for transmission back to the host. Thesecret key is never transmitted between the batteryand the host.Applications2.5G/3G Wireless HandsetsDigital Still and Video CamerasHandheld or Notebook Computers and TerminalsPDAs

EEPROM

The DS1220AB and DS1220AD 16k Nonvolatile (NV) SRAMs are 16,384-bit, fully static, NV SRAMs organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile (NV) SRAMs organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile (NV) SRAMs organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.