DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter Features: Quad integrated I/Q demodulator 16 phase select on each output (22.5° per step) Bandwidth: 4LO: LF to 200 MHz RF: LF to 50 MHz Baseband: determined by external filtering Power consumption: 73 mW/channel (290 mW total) Quadrature demodulation accuracy: Phase accuracy: ±1° Amplitude balance: ±0.25 dB Output dynamic range: 160 dB/Hz LO drive: >0 dBm (50 Ω), single-ended sine wave Supply: ±5 V Power-down via SPI (each channel and complete chip)

2 GHz Ultralow Distortion Differential RF/IF Amplifier Features: −3 dB bandwidth of 2.2 GHz (AV = +10 dB) Single resistor gain adjust: 3 dB ≤ AV ≤ 25 dB Single resistor and capacitor distortion adjust Input resistance: 3 kΩ, independent of gain (AV) Differential or single-ended input to differential output Low noise input stage: 2.7 nV/√Hz RTI at AV = 10 dB Low broadband distortion 10 MHz: −86 dBc HD2, −82 dBc HD3 70 MHz: −84 dBc HD2, −82 dBc HD3 190 MHz: −81 dBc HD2, −87 dBc HD3 OIP3 of 41 dBm at 150 MHz Slew rate: 8 V/ns Fast settling and overdrive recovery of <2 ns Single-supply operation: 3 V to 5.5 V Low power dissipation: 37 mA typical at 5 V Power-down capability: 5 mA at 5 V Fabricated using the high speed XFCB3 SiGe process

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

2GHz to 14GHz Microwave Mixer with Wideband DC6GHz IF Features: Upconversion or Downconversion High IIP3: +24.4dBm at 5.8GHz +21.4dBm at 9GHz 7.1dB Conversion Loss at 5.8GHz +15.2dBm Input P1dB at 5.8GHz Integrated LO Buffer: 0dBm LO Drive Selectable Integrated LO Frequency Doubler Low LO-RF Leakage: <–30dBm 50Ω Wideband Matched RF and LO Ports 3.3V/120mA Supply Fast Turn ON/OFF for TDD Operation 3mm × 2mm, 12-Lead QFN Package

300MHz to 9GHz High Linearity I/Q Demodulator with Wideband IF Amplifier Features: True Zero IF Demodulation Wideband Input Matched from 500MHz to 9GHz Wide IF Bandwidth: DC to 1GHz (1dB Flatness) 37dB Image Rejection, Adjustable to 60dB High Total OIP3: 37dBm at 5.8GHz 58dBm OIP2 at 5.8GHz, Adjustable to 65dBm Max Power Conversion Gain: 9.2dB at 5.8GHz Single-Ended RF Input with On-Chip Transformer User Adjustable DC Offset Null Serial Interface IF Amplifier Gain Adjustable in Eight Steps IF Amplifier Shutdown/Enable Low Power Shutdown Mode Operating Temperature Range (TC): −40°C to 105°C 32-Lead 5mm × 5mm QFN Package

High Linearity Differential RF/IF Amplifier/ADC Driver Features: 51.0dBm OIP3 at 240MHz into a 100Ω Diff Load NF = 2.9dB at 240MHz 20MHz to 2060MHz –3dB Bandwidth 20.8dB Gain A-Grade 100% OIP3 Tested at 380MHz 0.6nV/√Hz Total Input Noise S11 < –10dB Up to 1.4GHz S22 < –10dB Up to 1.4GHz >2.75VP-P Linear Output Swing P1dB = 24.0dBm Insensitive to VCC Variation 100Ω Differential Gain-Block Operation Input/Output Internally Matched to 100Ω Diff Single 5V Supply DC Power = 850mW 4mm × 4mm, 24-Lead QFN Package

HMC288MS8E series Attenuator Evaluation Board

SMT GaAs HBT MMIC Divide-by-4, DC - 12 GHz Features: Ultra Low SSB Phase Noise: -149 dBc/Hz Wide Bandwidth Output Power: -6 dBm Single DC Supply: +5V S8G SMT Package

High IP3 Mixer SMT, 450 - 500 MHz Features: Input IP3: +32 dBm Conversion Loss: 9.5 dB Low External Part Count Ultra Small MSOP8 Package: 14.8 mm²

RF Mixer