MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

2 GHz Ultralow Distortion Differential RF/IF Amplifier Features: −3 dB bandwidth of 2.2 GHz (AV = +10 dB) Single resistor gain adjust: 3 dB ≤ AV ≤ 25 dB Single resistor and capacitor distortion adjust Input resistance: 3 kΩ, independent of gain (AV) Differential or single-ended input to differential output Low noise input stage: 2.7 nV/√Hz RTI at AV = 10 dB Low broadband distortion 10 MHz: −86 dBc HD2, −82 dBc HD3 70 MHz: −84 dBc HD2, −82 dBc HD3 190 MHz: −81 dBc HD2, −87 dBc HD3 OIP3 of 41 dBm at 150 MHz Slew rate: 8 V/ns Fast settling and overdrive recovery of <2 ns Single-supply operation: 3 V to 5.5 V Low power dissipation: 37 mA typical at 5 V Power-down capability: 5 mA at 5 V Fabricated using the high speed XFCB3 SiGe process

LNA with Failsafe Bypass Mode SMT, 1700 - 2200 MHz Features: Noise Figure: 1.4 dB Output IP3: +29 dBm Gain: 17 dB Failsafe Operation: Bypass is enabled when LNA is unpowered Single Supply: +3V or +5V 16 Lead 3x3mm SMT Package: 9mm²

GaAs, pHEMT, MMIC, 1 W, Power Amplifier with Power Detector, 37 GHz to 40 GHz Features: 32 dBm typical saturated output power (PSAT) at 18% power added efficiency (PAE) at 39 GHz P1dB compression output power: 31.5 dBm typical High output third-order intercept (IP3): 40 dBm typical High gain: 24 dB typical 50 Ω matched input/output Ceramic, 6 mm × 6 mm, high frequency, air cavity package

Fractional-N PLL with Integrated VCO SMT, 1815 - 2010 MHz Features: RF Bandwidth: 1815 - 2010 MHz Fractional or Integer Modes 19-Bit Prescaler Ultra Low Phase Noise -110 dBc/Hz in Band Typ. Figure of Merit (FOM) -227 dBc Integer 24-Bit Step Size, 3 Hz Resolution Typ. 200 MHz, 14-bit Reference Path Input Cycle Slip Prevention 40 Lead 6x6mm SMT Package: 36mm²

Fractional-N PLL with Integrated VCO SMT, 1.31 - 5.66 GHz Features: Ultra Low Phase Noise -112 dBc/Hz in Band Typ. Figure of Merit (FOM) -230 dBc Integer <180 fs RMS Jitter  24-Bit Step Size, 3 Hz Resolution Typ.  Exact Frequency Mode Built in Digital Self Test  40 Lead 6x6mm SMT Package: 36mm²

Low Noise Amplifier, 0.4 GHz to 11 GHz Features: Low noise figure: 1.4 dB typical Single positive supply (self biased) High gain: ≤15.5 dB typical High OIP3: ≤33 dBm typical RoHS-compliant, 2 mm × 2 mm, 6-lead LFCSPHMC8412TCPZ-EP Supports defense and aerospace applications (AQEC standard) Download the HMC8412TCPZ-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/21602 DSCC Drawing Number

Analog Variable Gain Amplifier SMT, 5 - 12 GHz Features: Wide Gain Control Range: 22 dB Single Control Voltage: -1 to -4.5V Output IP3 @ Max Gain: +34 dBm Output P1dB: +22 dBm No External Matching 24 Lead 4x4 mm SMT Package: 16 mm²

Phase Detectors/Shifters 12-18 GHz Analog Phase Shifter

RF Amplifier SMT, lo Noise amp, DC - 20 GHz