The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.After digital processing, data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A.The AD6655 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Product Highlights Integrated dual, 14-bit, 150 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange detect and signal monitor with serial output. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS. SYNC input allows synchronization of multiple devices. 3-bit SPI port for register programming and register readback.Applications Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

The AD8302 is a fully integrated system for measuring gain/loss and phase in numerous receive, transmit, and instrumentation applications. It requires few external components and a single supply of 2.7 V–5.5 V. The ac-coupled input signals can range from –60 dBm to 0 dBm in a 50 Ω system, from low frequencies up to 2.7 GHz. The outputs provide an accurate measurement of either gain or loss over a ±30 dB range scaled to 30 mV/dB, and of phase over a 0°–180° range scaled to 10 mV/degree. Both subsystems have an output bandwidth of 30 MHz, which may optionally be reduced by the addition of external filter capacitors. The AD8302 can be used in controller mode to force the gain and phase of a signal chain toward predetermined setpoints. The AD8302 comprises a closely matched pair of demodulating logarithmic amplifiers, each having a 60 dB measurement range. By taking the difference of their outputs, a measurement of the magnitude ratio or gain between the two input signals is available. These signals may even be at different frequencies, allowing the measurement of conversion gain or loss. The AD8302 may be used to determine absolute signal level by applying the unknown signal to one input and a calibrated ac reference signal to the other. With the output stage feedback connection disabled, a comparator may be realized, using the setpoint pins MSET and PSET to program the thresholds.The signal inputs are single-ended, allowing them to be matched and connected directly to a directional coupler. Their input impedance is nominally 3 kΩ at low frequencies. The AD8302 includes a phase detector of the multiplier type, but with precise phase balance driven by the fully limited signals appearing at the outputs of the two logarithmic amplifiers. Thus, the phase accuracy measurement is independent of signal level over a wide range. The phase and gain output voltages are simultaneously available at loadable ground referenced outputs over the standard output range of 0 V to 1.8 V. The output drivers can source or sink up to 8 mA. A loadable, stable reference voltage of 1.8 V is available for precise repositioning of the output range by the user. In controller applications, the connection between the gain output pin VMAG and the setpoint control pin MSET is broken. The desired setpoint is presented to MSET and the VMAG control signal drives an appropriate external variable gain device. Likewise, the feedback path between the phase output pin VPHS and its setpoint control pin PSET may be broken to allow operation as a phase controller. The AD8302 is fabricated on Analog Devices’ proprietary, high performance 25 GHz SOI complementary bipolar IC process. It is available in a 14-lead TSSOP package and operates over a –40°C to +85°C temperature range. An evaluation board is available.

The ADF4360-8 is an integrated integer-N synthesizer and voltagecontrolled oscillator (VCO). The ADF4360-8 center frequencyis set by external inductors. This allows a frequencyrange of between 65 MHz to 400 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. 

The AD630 is a high precision balanced modulator/demodulatorthat combines a flexible commutating architecture with theaccuracy and temperature stability afforded by laser wafer trimmedthin film resistors. A network of on-board applications resistorsprovides precision closed-loop gains of ±1 and ±2 with 0.05%accuracy (AD630B). These resistors may also be used to accuratelyconfigure multiplexer gains of 1, 2, 3, or 4. External feedbackenables high gain or complex switched feedback topologies.The AD630 can be thought of as a precision op amp with twoindependent differential input stages and a precision comparatorthat is used to select the active front end. The rapid responsetime of this comparator coupled with the high slew rate and fastsettling of the linear amplifiers minimize switching distortion.The AD630 is used in precision signal processing and instrumentationapplications that require wide dynamic range. Whenused as a synchronous demodulator in a lock-in amplifierconfiguration, the AD630 can recover a small signal from100 dB of interfering noise (see the Lock-In AmplifierApplications section). Although optimized for operation up to1 kHz, the circuit is useful at frequencies up to several hundredkilohertz.Other features of the AD630 include pin programmable frequencycompensation; optional input bias current compensationresistors, common-mode and differential-offset voltage adjustment,and a channel status output that indicates which of thetwo differential inputs is active.Product Highlights The application flexibility of the AD630 makes it the best choice for applications that require precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high speed precision amplification. The 100 dB dynamic range of the AD630 exceeds that of any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments. The op amp format of the AD630 ensures easy implementation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts. The AD630 can be used as a 2-channel multiplexer with gains of 1, 2, 3, or 4. The channel separation of 100 dB at 10 kHz approaches the limit achievable with an empty IC package. Laser trimming of the comparator and amplifying channel offsets eliminate the need for external nulling in most cases.Applications Balanced modulation and demodulation Synchronous detection Phase detection Quadrature detection Phase sensitive detection Lock in amplification Square wave multiplication

The ADF4002 frequency synthesizer is used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the device can be used as a standalone PFD and charge pump.The ADF4002-EP supports defense and aerospace applications (AQEC standard).

The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. They consist of low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP+A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator).Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.

The LTC5530 is an RF power detector for RF applications operating in the 300MHz to 7GHz range. A temperature compensated Schottky diode peak detector and buffer amplifier are combined in a small ThinSOT™ package. The supply voltage range is optimized for operation from a single lithium-ion cell or 3xNiMH.The RF input voltage is peak detected using an on-chip Schottky diode. The detected voltage is buffered and supplied to the VOUT pin. The output buffer gain is set via external resistors. A power saving shutdown mode reduces current to less than 2µA.The LTC5530 operates with input power levels from -32dBm to 10dBm.*Higher frequency operation is achievable with reduced performance. Consult factory for more information.Applications 802.11a, 802.11b, 802.11g, 802.15, 802.16 Multimode Mobile Phone Products Optical Data Links Wireless Data Modems Wireless and Cable Infrastructure RF Power Alarm Envelope Detector

The ADF4355-2 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers permits operation from 54 MHz to 4400 MHz. The ADF4355-2 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4355-2 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains hardware and software power-down modes.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9361 is a high performance, highly integrated radiofrequency (RF) Agile Transceiver™ designed for use in 3G and4G base station applications. Its programmability and widebandcapability make it ideal for a broad range of transceiver applications.The device combines a RF front end with a flexible mixed-signalbaseband section and integrated frequency synthesizers, simplifyingdesign-in by providing a configurable digital interface to aprocessor. The AD9361 receiver LO operates from 70 MHz to6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHzrange, covering most licensed and unlicensed bands. Channelbandwidths from less than 200 kHz to 56 MHz are supported.The two independent direct conversion receivers have state-of-the-artnoise figure and linearity. Each receive (RX) subsystem includesindependent automatic gain control (AGC), dc offset correction,quadrature correction, and digital filtering, thereby eliminatingthe need for these functions in the digital baseband. The AD9361also has flexible manual gain modes that can be externallycontrolled. Two high dynamic range analog-to-digital converters(ADCs) per channel digitize the received I and Q signals and passthem through configurable decimation filters and 128-tap finiteimpulse response (FIR) filters to produce a 12-bit output signal atthe appropriate sample rate.The transmitters use a direct conversion architecture that achieveshigh modulation accuracy with ultralow noise. This transmitterdesign produces a best in class TX error vector magnitude (EVM)of <−40 dB, allowing significant system margin for the externalpower amplifier (PA) selection. The on-board transmit (TX)power monitor can be used as a power detector, enabling highlyaccurate TX power measurements.The fully integrated phase-locked loops (PLLs) provide lowpower fractional-N frequency synthesis for all receive andtransmit channels. Channel isolation, demanded by frequencydivision duplex (FDD) systems, is integrated into the design.All VCO and loop filter components are integrated.The core of the AD9361 can be powered directly from a 1.3 Vregulator. The IC is controlled via a standard 4-wire serial portand four real-time input/output control pins. Comprehensivepower-down modes are included to minimize power consumptionduring normal use. The AD9361 is packaged in a 10 mm × 10 mm,144-ball chip scale package ball grid array (CSP_BGA).Applications Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems