The ADL5541 is a broadband 15 dB linear amplifier that operates at frequencies up to 6 GHz. The device can be used in a wide variety of CATV, cellular, and instrumentation equipment. The ADL5541 provides a gain of 15 dB, which is stable over frequency, temperature, power supply, and from device to device. The device is internally matched to 50 Ω with an input return loss of 10 dB or better up to 6 GHz. Only input/output ac coupling capacitors, power supply decoupling capacitors, and an external inductor are required for operation. The ADL5541 is fabricated on an InGaP HBT process and has an ESD rating of 1 kV (Class 1C). The device is packaged in a 3 mm × 3 mm LFCSP that uses an exposed paddle for excellent thermal impedance. The ADL5541 consumes 90 mA on a single 5 V supply and is fully specified for operation from −40°C to +85°C. A fully populated RoHS-compliant evaluation board is available. The ADL5542 is a companion part that offers a gain of 20 dB in a pin-compatible package. 

The LT5579 mixer is a high performance upconverting mixer optimized for frequencies in the 1.5GHz to 3.8GHz range. The single-ended LO input and RF output ports simplify board layout and reduce system cost. The mixer needs only –1dBm of LO power and the balanced design results in low LO signal leakage to the RF output. At 2.6GHz operation, the LT5579 provides high conversion gain of 1.3dB, high OIP3 of +26dBm and a low noise floor of –157.5dBm/Hz at a –5dBm RF output signal level. The LT5579 offers a high performance alternative to passive mixers. Unlike passive mixers, which have conversion loss and require high LO drive levels, the LT5579 delivers conversion gain at significantly lower LO input levels and is less sensitive to LO power level variations. The lower LO drive level requirements, combined with the excellent LO leakage performance, translate into lower LO signal contamination of the output signal.Applications GSM/EDGE, W-CDMA, UMTS, LTE and TD-SCDMA Basestations 2.6GHz and 3.5GHz WiMAX Basestations 2.4GHz ISM Band Transmitters High Performance Transmitters

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.After digital processing, data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A.The AD6655 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Product Highlights Integrated dual, 14-bit, 150 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange detect and signal monitor with serial output. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS. SYNC input allows synchronization of multiple devices. 3-bit SPI port for register programming and register readback.Applications Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The ADF4355-2 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers permits operation from 54 MHz to 4400 MHz. The ADF4355-2 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4355-2 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains hardware and software power-down modes.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency.The ADF4151 is used with external VCO parts and is footprint and software compatible with the ADF4350. The part consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider [N = (INT + (FRAC/MOD))]. The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4151 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V that can be powered down when not in use.The ADF4151 is available in a 5 mm × 5 mm package.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

The ADRF6518 is a matched pair of fully differential low noise and low distortion programmable filters and variable gain amplifiers (VGAs). Each channel is capable of rejecting large out-of-band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog-to-digital converters (ADCs). The excellent matching between channels and their high spurious-free dynamic range over all gain and bandwidth settings make the ADRF6518 ideal for quadrature-based (IQ) communication systems with dense constellations, multiple carriers, and nearby interferers. The various amplifier gains, filter corners and other features are all programmable via a serial port interface (SPI) port.The first VGA that precedes the filters offers 24 dB of continuous gain control with fixed gain options of 9 dB, 12 dB, and 15 dB, and sets a differential input impedance of 400 Ω. The filters provide a six-pole Butterworth response with 0.5 dB corner frequencies from 1 MHz to 63 MHz in 1 MHz steps. For operation beyond 63 MHz, the filter can be disabled and completely bypassed, thereby extending the −3 dB BW up to 1100 MHz. A wideband peak detector is available to monitor the peak signal at the filter inputs. The pair of VGAs that follow the filters each provides 24 dB of continuous gain control with fixed gain options of 12 dB, 15 dB, 18 dB, and 21 dB. The output buffers offer an additional option of 3 dB or 9 dB gain and provide a differential output impedance of less than 10 Ω. They are capable of driving 1.5 V p-p into 400 Ω loads at better than 65 dBc HD3. The output common-mode voltage defaults to VPS/2 and can be adjusted down to 900 mV via the VOCM pin. Independent, built-in dc offset correction loops for each channel can be disabled via the SPI if fully dc-coupled operation is desired. The high-pass corner frequency is determined by external capacitors on the OFS1 and OFS2 pins and the postfilter VGA gain.The ADRF6518 operates from a 3.15 V to 3.45 V supply and consumes a maximum supply current of 400 mA. When fully disabled, it consumes <1 mA. The ADRF6518 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead, exposed pad LFCSP. Performance is specified over the −40°C to +85°C temperature range.Applications Point-to-point and point-to-multipoint radios Baseband I/Q receivers Diversity receivers ADC drivers Instrumentation Medical

RF Mixer GaAs MMIC Sub-Harmonic mix, 54 - 64 GHz

RF Amplifier

Buffer Amplifier 1 Circuit Differential SOT-6