RF Modules Ultralo PhaseNoise Dist amp Modul2-18GHz

RF Amplifier lo Noise amp Chip, 23 - 32 GHz

RF Amplifier GaAs HEMT WBand lo Noise amp, 14-27 GHz

Data Conversion IC Development Tools LTC2217IUP LVDS OUT, 105Msps, 16-Bit ADC 70MHz < Ain < 140MHz, (req. DC890 & LVDS_XFMR)

RF Amplifier GaAs HEMT WBand lo Noise amp, 18-40 GHz

RF Switch ICs SP4T Positive Control Swt , DC - 8 GHz

The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.The AD9251 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).PRODUCT HIGHLIGHTS The AD9251 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. The AD9251 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

The AD9261 is a 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta (Σ-Δ) architecture that achieves 86 dB of dynamic range over a 10 MHz input bandwidth. The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components.The AD9261 has a resistive input impedance that significantly relaxes the requirements of the driver amplifier. In addition, a 32× oversampled 5th-order continuous time loop filter significantly attenuates out of band signals and aliases, reducing the need for external filters at the input.An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate between 30 MSPS to 160 MSPS, enabling a more efficient and direct interface.The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic.The AD9261 operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 375 mW. The AD9261 is available in a 48-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C).Product Highlights Continuous time Σ-Δ architecture efficiently achieves high dynamic range and wide bandwidth. Passive input structure reduces or eliminates the requirements for a driver amplifier. An oversampling ratio of 32× and high order loop filter provide excellent alias rejection reducing or eliminating the need for antialiasing filters. An integrated decimation filter, sample rate converter, PLL clock multiplier, and voltage reference provide ease of use. Operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply. A standard serial port interface (SPI) supports various product features and functions.Applications Data Acquisition Automated Test Equipment Instrumentation Medical Imaging

The AD9522-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.   The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.The AD9522 is specified for operation over the standard industrial range of −40°C to +85°C.The AD9520-5 is an equivalent part to the AD9522-5 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific member of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

The AD9704/AD9705/AD9706/AD9707 are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI®) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTS Pin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package). Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding. Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate. Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability. Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference. Industry-Standard 32-Lead LFCSP Package.