Variable Resolution Resolver-to-Digital Converter Features: Tracking R/D Converter High Accuracy Velocity Output High Max Tracking Rate 1040 RPS (10 Bits) 44-Lead PLCC Package 10-, 12-, 14-, or 16-Bit Resolution Set by User Ratiometric Conversion Stabilized Velocity Reference Dynamic Performance Set by User Industrial Temperature Range

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs, Open Wire Detection Features: Tested for robustness per: IEC6100-4-2, IEC6100-4-3, IEC6100-4-4, IEC6100-4-5, IEC6100-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C Open wire detection 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with 10 V Inputs Features:24-bit ADC with integrated AFEFast and flexible output rate: 2.5 SPS to 125 kSPSChannel scan data rate of 24,845 SPS per channel (40.25 s settling)85 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel10 V inputs, either 8 differential or 16 single-endedVIN pin absolute maximum rating 65 VAbsolute input pin voltage up to 20 VMinimum 1 M impedanceOn-chip 2.5 V reference0.12% initial accuracy at 25C, 5 ppm/C (typical) driftInternal or external clockPower suppliesAVDD = 4.5 V to 5.5 VIOVDD = 2 V to 5.5 VTotal current consumption AVDD + IOVDD (IDD) = 10.4 mATemperature range: 40C to +105C3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)SPI, QSPI, MICROWIRE, and DSP compatible

Fully Accurate 12-Bit VOUT nanoDAC SPI Interface 4.5 V to 5.5 V in a TSSOP Features: Low power dual 12-/14-/16-bit DAC, ±1 LSB INL Individual voltage reference pins Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale Power down to 400 nA at 5 V 3 power-down functions Per channel power-down Low glitch upon power-up Hardware power-down lockout capability Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option 14-lead TSSOP

256 Position SPI/I2C Selectable Digital Potentiometer Features: 256-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Compact MSOP-10 (3 mm × 4.9 mm) package Pin selectable SPI/I2C compatible interface Extra package address decode pin AD0 Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 8 μA Wide operating temperature −40°C to +125°C SDO output allows multiple device daisy-chaining Evaluation board available

Dual, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Features: Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch