SigmaDSP Multichannel 28-Bit Audio Processor Features: 16-channel digital audio processor Accepts sample rates up to 192 kHz 28-bit × 28-bit multiplier with full 56-bit accumulator Fully programmable program RAM for custom program download Parameter RAM allows complete control of 1,024 parameters Control port features safeload for transparent parameter updates and complete mode and memory transfer control Target/slew RAM for click-free volume control and dynamic parameter updates See data sheet for additional features

16 Input/16 Output Analog I/O Port With Integrated Amplifiers Features: Operational amplifiers Offset voltage: 2.2 mV maximum Low input bias current: 1 pA maximum Single supply operation Low noise: 22 nV/√Hz Unity gain stable Available in 80-ball CSP_BGA package See Datasheet for additional features

Dual Low Power, 14-Bit TxDAC Digital-to-Analog Converters Features:Power dissipation @ 3.3 V, 20 mA output191 mW @ 10 MSPS 232 mW @ 125 MSPSSleep mode: Supply voltage: 1.8 V to 3.3 VSFDR to Nyquist86 dBc @ 1 MHz output 85 dBc @ 10 MHz outputNSD @ 10 MHz output, 125 MSPS, 20 mA: 157 dBc/HzDifferential current outputs: 4 mA to 20 mA2 on-chip auxiliary DACsCMOS inputs with single-port operationOutput common mode: adjustable 0 V to 1.2 VSmall footprint 40-lead LFCSP RoHS-compliant package

20 MHz to 6 GHz RF/IF Gain Block, Fixed Gain of 15 dB Features: Fixed gain of 15 dB  Operation up to 6 GHz  Input/output internally matched to 50 Ω  Integrated bias control circuit  Output IP3 44 dBm at 500 MHz 40 dBm at 900 MHz  Output 1 dB compression: 19.7 dBm at 900 MHz  Noise figure of 3.5 dB at 900 MHz  Single 5 V power supply  Small footprint 8-lead LFCSP  Pin compatible with 20 dB gain ADL5542  1 kV ESD (Class 1C) 

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC Features: Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Proprietary dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate BERMON or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP

Dual 260 MHz Gain = +2.0 & +2.2 Buffer Data Sheet  

0.5 Ω CMOS 1.65 V TO 3.6 V Dual SPDT/2:1 MUX Data Sheet  

14-Bit, 300 MSPS High-Speed TxDAC+® D/A Converter Data Sheet 

2.5 V/3.3 V, 16 Bit, 2 Port Level Translator, Bus Switch Data Sheet  

Complete Dual, 16-Bit High Accuracy, Serial Input, ±5 V DAC Data Sheet