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Texas Instruments
OMAP3530ECBB
|
Texas Instruments
SN74LS27DR
|
Texas Instruments
SN65LVDS9637DGNR
|
Texas Instruments
CDC2536DBRG4
|
Texas Instruments
REG1117FA5.0/500G3
|
Texas Instruments
UCC3960DG4
|
Texas Instruments
SN74LVC00ADR
|
Texas Instruments
LM3S2965-EQC50-A2T
|
Texas Instruments
OPA2343UA/2K5G4
|
Texas Instruments
TLC274IN
|
| Price |
|
|
$0.58 |
|
|
|
|
$0.16 |
$10.81 |
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| RoHS |
|
Yes |
Yes |
Yes |
Compliant |
Compliant |
Compliant |
Yes |
Compliant |
Compliant |
Yes |
| Lead Status |
|
Yes |
Yes |
Yes |
No |
No |
No |
Yes |
No |
No |
Yes |
| Memory Interface (Dual Channel) |
|
1 16-bit LPDDR , 1 32-bit SDRC |
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| Approx. Price (US$) |
|
52.08 | 100u |
0.35 | 1ku |
0.84 | 1ku |
4.20 | 1ku |
1.53 | 1ku |
1.40 | 1ku |
0.08 | 1ku |
|
1.00 | 1ku |
0.55 | 1ku |
| ARM MHz (Max.) |
|
720 |
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| Process Node |
|
65nm |
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| Performance |
|
D1 |
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| Integrated TI C64x DSP |
|
Up to 520 MHz |
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| 2D & 3D Graphics |
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Hardware Accelerated |
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| ARM CPU |
|
1 ARM Cortex-A8 |
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| Operating Temperature Range(C) |
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|
0 to 70 |
-40 to 85 |
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0 to 70 |
-40 to 125 |
|
-40 to 85 |
-40 to 85,-55 to 125,0 to 70 |
| Technology Family |
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LS |
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LVC |
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| Rating |
|
|
Catalog |
|
Catalog |
Catalog |
Catalog |
Catalog |
|
Catalog |
Catalog |
| Output Drive (IOL/IOH)(Max)(mA) |
|
|
0.8/-16 |
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|
24/-24 |
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| Schmitt Trigger |
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|
No |
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No |
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| VCC(Max)(V) |
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|
5.25 |
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3.6 |
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| F @ Nom Voltage(Max)(Mhz) |
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|
35 |
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|
150 |
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| Voltage(Nom)(V) |
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|
5 |
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1.8,2.5,2.7,3.3 |
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| Package Group |
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|
PDIP,SOIC,SO |
MSOP-PowerPAD,SOIC,VSSOP |
SSOP |
DDPAK/TO-263 |
PDIP,SOIC |
SO,SOIC,SSOP,VQFN,TSSOP |
|
SOIC,VSSOP |
PDIP,SO,SOIC,SSOP,TSSOP |
| Package Size |
|
|
mm2 |
mm2 |
mm2 |
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|
mm2 |
|
mm2 |
mm2 |
| tpd @ Nom Voltage(Max)(ns) |
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15 |
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12.5,6.4,5.1,4.3 |
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| VCC(Min)(V) |
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|
4.75 |
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1.65 |
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| ICC @ Nom Voltage(Max)(mA) |
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|
0.026 |
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|
0.04 |
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| Bits(#) |
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|
3 |
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4 |
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| ICC(Max)(mA) |
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|
10 |
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| Output Signal |
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LVTTL |
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| Function |
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|
Receiver |
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| Input Signal |
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|
LVDS |
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| No. of Rx |
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2 |
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| Signaling Rate(Mbps) |
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|
150 |
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| ESD HBM(kV) |
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|
8 |
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| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)(ps) |
|
|
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|
200 |
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| Number of Outputs |
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6 |
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| tsk(o)(ps) |
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500 |
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| t(phase error)(ps) |
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500 |
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| Operating Frequency Range(Min)(MHz) |
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25 |
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| VCC(V) |
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|
3.3 |
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| Operating Frequency Range(Max)(MHz) |
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|
100 |
|
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| Estimated Package Size (WxL)(mm2) |
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|
[pf]3DDPAK/TO-263[/pf] |
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| PSRR @ 100KHz(dB) |
|
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|
29 |
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| Output Options |
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|
Adjustable Output,Fixed Output |
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| Fixed Output Options(V) |
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5 |
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| Vin(Min)(V) |
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3.8 |
16 |
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| Iout(Max)(A) |
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|
1 |
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| Regulated Outputs(#) |
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|
1 |
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| Iq(Typ)(mA) |
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4 |
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| Vin(Max)(V) |
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|
15 |
19 |
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| Vdo(Typ)(mV) |
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|
1200 |
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| Vout(Max)(V) |
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|
5 |
|
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| Vout(Min)(V) |
|
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|
5 |
|
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| Features |
|
|
|
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|
N/A |
|
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|
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| Frequency(Max)(kHz) |
|
|
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|
400 |
|
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|
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| UVLO Thresholds On/Off(V) |
|
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|
10.0/8.0 |
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| Gate Drive(Typ)(A) |
|
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|
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|
1.5 |
|
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|
|
| Topology |
|
|
|
|
|
|
N/A |
|
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|
|
| Control Method |
|
|
|
|
|
|
Current |
|
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|
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| Duty Cycle(Max)(%) |
|
|
|
|
|
|
72 |
|
|
|
|
| Output Current(Typ)(mA) |
|
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|
|
|
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|
50 |
10 |
| GBW(Typ)(MHz) |
|
|
|
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|
5.5 |
0.32 |
| Iq per channel(Typ)(mA) |
|
|
|
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|
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|
0.85 |
0.675 |
| Vn at 1kHz(Typ)(nV/rtHz) |
|
|
|
|
|
|
|
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|
25 |
25 |
| Total Supply Voltage(Min)(+5V=5, +/-5V=10) |
|
|
|
|
|
|
|
|
|
2.5 |
3 |
| Iq per channel(Max)(mA) |
|
|
|
|
|
|
|
|
|
1.25 |
1.6 |
| IIB(Max)(pA) |
|
|
|
|
|
|
|
|
|
10 |
|
| Architecture |
|
|
|
|
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|
|
CMOS |
CMOS |
| Rail-to-Rail |
|
|
|
|
|
|
|
|
|
In,Out |
In to V- |
| Number of Channels(#) |
|
|
|
|
|
|
|
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|
2 |
4 |
| CMRR(Min)(dB) |
|
|
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|
|
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|
74 |
65 |
| Vos (Offset Voltage @ 25C)(Max)(mV) |
|
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|
8 |
10 |
| Total Supply Voltage(Max)(+5V=5, +/-5V=10) |
|
|
|
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|
|
5.5 |
16 |
| Offset Drift(Typ)(uV/C) |
|
|
|
|
|
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|
|
|
3 |
1.8 |
| Slew Rate(Typ)(V/us) |
|
|
|
|
|
|
|
|
|
6 |
3.6 |
| Additional Features |
|
|
|
|
|
|
|
|
|
N/A |
N/A |
| CMRR(Typ)(dB) |
|
|
|
|
|
|
|
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|
92 |
80 |
| Input Bias Current(Max)(pA) |
|
|
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|
10 |
60 |
