50 V, 1 MHz, 165 A per Channel, Robust, Over-The-Top, Precision Op Amps Features: Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: +3 V to +50 V (to ±25 V for PSRR) Low power supply current: 165 μA per channel (typical) Low input offset voltage: ±35 μV maximum Low input offset voltage drift: ±0.5 μV/°C maximum (B grade) Low input voltage noise 1/f noise corner: 6 Hz typical 400 nV p-p typical at 0.1 Hz to 10 Hz 17 nV/√Hz typical at 100 Hz High speed GBP: 1.05 MHz typical for fTEST = 2.5 kHz Slew rate: 0.85 V/μs typical at ΔVOUT = 25 V Low power supply current shutdown: 20 μA maximum Low input offset current: ±700 pA maximum Large signal voltage gain: 126 dB minimum for ΔVOUT = 3.5 V CMRR: 120 dB minimum at VCM = −0.1 V to +70 V PSRR: 123 dB minimum at VSY = +3 V to ±25 V Input overdrive tolerant with no phase reversal ±3 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade)

50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps Features: Ultrawide common-mode range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: (VSY): +3.15 V to +50 V (±25 V for PSRR) Low supply current: 1.5 mA per channel (typical) Low input offset voltage: ±40 μV maximum Low input offset voltage drift: ±0.4 μV/°C maximum Low voltage noise: 1/f noise corner: 6 Hz typical 150 nV p-p typical at 0.1 Hz to 10 Hz 7 nV/√Hz typical at 100 Hz (en) High speed GBP: 8 MHz typical Slew rate: 5.5 V/μs typical at ΔVOUT = 25 V Low power shutdown: 20 μA maximum Low input bias current: ±10 nA maximum Large signal voltage gain: 120 dB minimum CMRR: 118 dB, minimum PSRR: 123 dB, minimum Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade)

OVP and EMI Protected, Precision, Low Noise and Bias Current Single Op Amp Features: Low offset voltage: 60 μV maximum at 25°C (8-lead and 14-lead SOIC) Low offset voltage drift: 1 μV/°C maximum (8-lead and 14-lead SOIC) Low input bias current: 1 nA maximum at 25°C Low voltage noise density: 8 nV/√Hz typical at 1 kHz Large signal voltage gain (AVO): 100 dB minimum over full supply voltage and operating temperature Input overvoltage protection to 32 V above and below the supply voltage rail Integrated EMI filter 70 dB typical rejection at 1000 MHz 90 dB typical rejection at 2400 MHz Rail-to-rail output swing Low supply current: 500 μA typical per amplifier Wide bandwidth Gain bandwidth product (AV = 100): 3.5 MHz typical Unity-gain crossover (AV = 1): 3.5 MHz typical −3 dB bandwidth (AV = 1): 6 MHz typical Dual-supply operation Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V Unity-gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 2 μV typical Temperature hysteresis: 2 μV typical

Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier Features: Optimized for ADC synchronization Low power: 22 mW (±12 V supplies) 12 binary gain steps from 1/16 V/V to 128 V/V 3 scaling gains: 1 V/V, 1.25 V/V, and 1.375 V/V ±60 V protected input multiplexer Excellent dc precision Low input offset voltage: ±14 μV maximum Low input offset voltage drift: ±0.08 μV/°C maximum Gain calibration via ROM Low gain drift: ±1 ppm/°C maximum High CMRR: 116 dB minimum, G = 1 V/V Low input bias current: ±1.5 nA maximum High input impedance Integrated input EMI filtering Wide input supply range: ±5 V to ±28 V Dedicated output amplifier supplies 7 GPIO ports with special functions Sequential chip select mode External multiplexer control Excitation current sources SPI port with checksum (CRC) support Internal fault detection Wire break test currents On-chip test multiplexer 28-lead, 5 mm × 5 mm LFCSP, 24-lead TSSOP Specified temperature range: −40°C to +105°C

Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier Features: Optimized for ADC synchronization Low power: 22 mW (±12 V supplies) 12 binary gain steps from 1/16 V/V to 128 V/V 3 scaling gains: 1 V/V, 1.25 V/V, and 1.375 V/V ±60 V protected input multiplexer Excellent dc precision Low input offset voltage: ±14 μV maximum Low input offset voltage drift: ±0.08 μV/°C maximum Gain calibration via ROM Low gain drift: ±1 ppm/°C maximum High CMRR: 116 dB minimum, G = 1 V/V Low input bias current: ±1.5 nA maximum High input impedance Integrated input EMI filtering Wide input supply range: ±5 V to ±28 V Dedicated output amplifier supplies 7 GPIO ports with special functions Sequential chip select mode External multiplexer control Excitation current sources SPI port with checksum (CRC) support Internal fault detection Wire break test currents On-chip test multiplexer 28-lead, 5 mm × 5 mm LFCSP, 24-lead TSSOP Specified temperature range: −40°C to +105°C

Bridge Sensor Signal Conditioner IC with LIN Interface, Nonlinearity Correction, Temperature Compensation Features:LIN 2.1 compliant interface (bridge sensor signal, temperature)Digitally programmable gain and offset voltage adjustmentGain range from 2.94 V/V to 971.10 V/VSensor temperature compensation (first- or second-order)Sensor nonlinearity correction (first- or second-order)Internal or external temperature sensor compensationEEPROM nonvolatile memory for calibration dataHigh system accuracy: 0.1% FSR over temperatureEMC and EMI protectionFault protection for open circuits and short circuits4 mm 4 mm, 20-lead LFCSP6 V to 18 V supply operation40C to +150C operating temperature rangeAEC-Q100 qualified for automotive applications

Integrated AMR Angle Sensor and Signal Conditioner with Differential Outputs Features: Contactless angular measurement High precision 180° angle sensor Typical angular error of ±0.1° Low output noise of 850 μV rms Sine and cosine differential outputs Ratiometric analog voltage outputs Negligible hysteresis SAR or Σ-Δ ADC compatible Temperature compensated AMR bridge Industrial temperature range: −40°C to +125°C Automotive temperature range: −40°C to +150°C EMI resistant Fault diagnostics VDD from 2.7 V to 5.5 V Minimal phase error of 0.85° at 30,000 rpm AEC-Q100 qualified for automotive applications Single chip solution Available in an 8-lead SOIC package

Integrated AMR Angle Sensor and Signal Conditioner with Differential Outputs Features: Contactless angular measurement High precision 180° angle sensor Typical angular error of ±0.1° Low output noise of 850 μV rms Sine and cosine differential outputs Ratiometric analog voltage outputs Negligible hysteresis SAR or Σ-Δ ADC compatible Temperature compensated AMR bridge Industrial temperature range: −40°C to +125°C Automotive temperature range: −40°C to +150°C EMI resistant Fault diagnostics VDD from 2.7 V to 5.5 V Minimal phase error of 0.85° at 30,000 rpm AEC-Q100 qualified for automotive applications Single chip solution Available in an 8-lead SOIC package

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

150 mA, Low Dropout, CMOS Linear Regulator Features: Maximum output current: 150 mA Input voltage range: 2.5 V to 5.5 V Light load efficient IGND = 35 μA with zero load IGND = 40 μA with 100 μA load Low shutdown current: <1 μA Low dropout voltage: 150 mV @ 150 mA load Initial accuracy: ±1% Accuracy over line, load, and temperature: ±2% Stable with small 1 μF ceramic output capacitor 16 fixed output voltage options: 0.75 V to 3.3 V (ADP1710) Adjustable output voltage option: 0.8 V to 5.0 V (ADP1710 Adjustable) 16 fixed output voltage options with reference bypass: 0.75 V to 3.3 V (ADP1711) High PSRR: 69 dB @ 1 kHz