Microprocessor Supervisory Circuit in 3-Lead SC70, Active-Low Open-Drain Output Features: Specified over temperature Low power consumption (17 μA) Precision voltage monitor: 2.5 V, 3 V, 3.3 V, 5 V options Reset assertion down to 1 V VCC 140 ms minimum power-on reset Open-drain RESET output

Ultralow Power Voltage Detector with Disable Input and Low Threshold Voltages Features: Ultralow power consumption with ICC = 92 nA (typical) Precision, low voltage monitoring Pretrimmed voltage monitoring threshold options 20 options from 0.5 V to 1.9 V ±1.3% threshold accuracy over full temperature range Output disable input 23 µs to 26 µs typical propagation delay Open-drain type output Power supply glitch immunity Available in a 1.46 mm × 0.96 mm WLCSP Operational temperature range: −40°C to +85°C

15.1 GHz to 32 GHz, Tunable Band-Pass Filter Features:Amplitude settling time: 200 ns typicalWideband rejection: 30 dBSingle chip implementation40-lead, 6 mm 6 mm, RoHS compliant LFCSP

2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter Features: Digitally tunable, multioctave, high-pass and low-pass tuning Independent 3 dB frequency control for up to 4 GHz of bandwidth Optimal wideband rejection: 35 dB Single chip replacement for discrete filter banks Compact 9 mm × 9 mm, 56-terminal LGA packageENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard Military temperature range of −55°C to +105°C Controlled manufacturing baseline One assembly and test site One fabrication site Production change notification Qualification data available on request V62/21604

5.7 kV RMS/1.5 kV RMS, Quad-Channel LVDS 2.5 Gigabit Isolator (0 Reverse Channels) Features: 5.7 kV rms and 1.5 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS signal levels Quad-channel configuration Any data rate up to 2.5 Gbps switching with low jitter 10 Gbps total bandwidth across four channels 2.15 ns typical propagation delay Typical jitter: 0.82 ps rms random, 40 ps total peak Lower power 1.8 V supplies ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: 100 kV/μs typical Safety and regulatory approvals (28-lead SOIC_W_FP package) UL (pending): 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 VIORM = 849 VPEAK (working voltage) Enable or disable refresh (low speed output correctness check) Operating temperature range: −40°C to +125°C 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance or 6 mm × 6 mm LFCSP package with 1.27 mm creepage and clearance

5 kV RMS/3.75 kV RMS, Dual LVDS Gigabit Isolator (0 Reverse Channels) Features: 5 kV rms and 3.75 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Any data rate up to 1.1 Gbps switching with low jitter 4 ns typical propagation delay 2.6 ps rms typical random jitter, rms 90 ps typical peak-to-peak total jitter at 1.1 Gbps 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection, phase spur level Glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with 1.1 Gbps PRBS Safety and regulatory approvals (20-lead SOIC_W package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VPEAK Fail-safe output high for open, short, and terminated input conditions (ADN4655/ADN4656) Operating temperature range: −40°C to +125°C 7.8 mm minimum creepage and clearance

Digital Controller for Power Supply Applications with PMBus Interface Features: −40°C to +125°C operation with EEPROM data retention of 15 years at 125°C PMBus Revision 1.2 compliant 32-bit password protection with command masking 64 address selections (16 base addresses, expandable to 64) 6 PWM control signals, 625 ps resolution Duty cycle double update rate Digital control loop (PID + additional pole or zero configurability) Programmable loop filters (CCM, DCM, low/normal temperature) Frequency synchronization Soft start and soft stop functionality Average and peak constant current mode External PN junction temperature sensing 4 GPIOs (2 GPIOs configurable as active clamp snubber PWMs) Fast line voltage feedforward Adaptive dead time compensation for improved efficiency Extended black box data recorder for fault recording See datasheet for additional features

Digital Controller for Power Supply Applications with PMBus Interface Features: −40°C to +125°C operation with EEPROM data retention of 15 years at 125°C PMBus Revision 1.2 compliant 32-bit password protection with command masking 64 address selections (16 base addresses, expandable to 64) 6 PWM control signals, 625 ps resolution Duty cycle double update rate Digital control loop (PID + additional pole or zero configurability) Programmable loop filters (CCM, DCM, low/normal temperature) Frequency synchronization Soft start and soft stop functionality Average and peak constant current mode External PN junction temperature sensing 4 GPIOs (2 GPIOs configurable as active clamp snubber PWMs) Fast line voltage feedforward Adaptive dead time compensation for improved efficiency Extended black box data recorder for fault recording See datasheet for additional features

Isolated Synchronous Flyback Controller with Integrated iCoupler Features: Current mode controller for flyback topology ADP1071-1: programmable LLM or CCM for high VIN applications ADP1071-2: forced CCM operation Programmable slope compensation Integrated 5 kV isolation (wide body SOIC package) or 3.0 kV (LGA package) rated dielectric isolation voltage with Analog Devices, Inc., patented iCoupler technology Wide voltage supply range Primary VDD: up to 60 V (ADP1071-2 only) Secondary VDD2: up to 36 V Integrated 1 A primary side MOSFET driver Integrated 1 A secondary side MOSFET drivers for synchronous rectification Integrated error amplifier and <1% accurate reference voltage Programmable frequency range: 50 kHz to 600 kHz Duty cycle clamp limit 85% Programmable soft start and soft start from precharged load Protection features such as short circuit, output overvoltage, and overtemperature protection Power saving LLM using MODE pin (ADP1071-1only) Cycle by cycle input overcurrent protection Precision enable UVLO with hysteresis Frequency synchronization Safety and regulatory approvals (pending) UL recognition 5000 V rms for 1 minute per UL 1577 (for wide body SOIC package) 3000 V rms for 1 minute per UL 1577 (for LGA package) CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak (for wide body SOIC package) VIORM = 565 V peak (for LGA package) CQC certification per GB4943.1-2011 Available in 16-lead SOIC_W package and 24 terminal LGA package

Ultralow Noise, 150 mA CMOS Linear Regulator Features: Chinese data sheet available Ultralow noise: 9 μV rms, independent of VOUT No additional noise bypass capacitor required Stable with 1 μF ceramic input and output capacitors Maximum output current: 150 mA Input voltage range: 2.2 V to 5.5 V Low quiescent current IGND = 10 μA with zero load Low shutdown current: <1 μA Low dropout voltage: 105 mV at 150 mA load Initial output voltage accuracy: ±1% Up to 14 fixed output voltage options: 1.8 V to 3.3 V PSRR performance of 70 dB at 10 kHz Current limit and thermal overload protection Logic-controlled enable 5-lead TSOT package 4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP AEC-Q100 qualified for automotive applications