The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (?-?) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G FDD, macrocell base stations Wide band active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC?with an integrated power amplifier, low noise amplifier (LNA), and a reflective single-pole double-throw (SPDT) switch. These?integrated features make the device ideal for phased array antenna and radar applications. The front-end IC offers 25 dBm of saturated output power (PSAT) and 22?dB small signal gain in?transmit state, and 18 dB small signal gain and 2.5 dB noise figure in receive state. The device has a directional coupler for power detection. The input/outputs (I/Os) are internally matched to 50 ?. The ADTR1107 is supplied in a 5 mm ? 5 mm, 24-terminal, land grid array (LGA) package.Applications Phased array antenna Military radar Weather radar Communication links Electronic warfare

The ADXL203 is a high precision, low power, complete dual-axis accelerometer with signal conditioned voltage outputs, all on a single, monolithic IC. The ADXL203 measures acceleration with a full-scale range of ?1.7 g, ?5 g, or ?18 g. The ADXL203 can measure both dynamic acceleration (for example, vibration) and static acceleration (for example, gravity).The typical noise floor is 110 ?g/?Hz, allowing signals below 1 mg (0.06? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (<60 Hz). The user selects the bandwidth of the accelerometer using Capacitor CX and Capacitor CY at the XOUT and YOUT pins. Bandwidths of 0.5 Hz to 2.5 kHz can be selected to suit the application.The ADXL203 is available in a 5 mm ? 5 mm ? 2 mm, 8-terminal ceramic LCC package.Applications: Platform stabilization/leveling Navigation Alarms and motion detectors High accuracy, 2-axis tilt sensing Vibration monitoring and compensation Abuse event detection

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The ADP2105 / ADP2106 / ADP2107 are low quiescent current,synchronous, step-down dc-to-dc converters in a compact 4 mm ?4 mm LFCSP package. At medium to high load currents, thesedevices use a current mode, constant frequency pulse-widthmodulation (PWM) control scheme for excellent stability andtransient response. To ensure the longest battery life in portableapplications, the ADP2105 / ADP2106 / ADP2107 use a pulsefrequency modulation (PFM) control scheme under light loadconditions that reduces switching frequency to save power.The ADP2105 / ADP2106 / ADP2107 run from input voltages of2.7 V to 5.5 V, allowing single Li+/Li? polymer cell, multiplealkaline/NiMH cells, PCMCIA, and other standard power sources.The output voltage of ADP2105 / ADP2106 / ADP2107 is adjustablefrom 0.8 V to the input voltage (indicated by ADJ), whereas theADP2105 / ADP2106 / ADP2107 are available in preset outputvoltage options of 3.3 V, 1.8 V, 1.5 V, and 1.2 V (indicated by x.x V).Each of these variations is available in three maximum currentlevels: 1 A (ADP2105), 1.5 A (ADP2106), and 2 A (ADP2107).The power switch and synchronous rectifier are integrated forminimal external part count and high efficiency. During logiccontrolled shutdown, the input is disconnected from the output,and it draws less than 0.1 ?A from the input source. Other keyfeatures include undervoltage lockout to prevent deep batterydischarge and programmable soft start to limit inrush current atstartup.Applications Mobile handsets PDAs and palmtop computers Telecommunication/networking equipment Set top boxes Audio/video consumer electronics

ADC, 12-BIT, 250MSPS, LFCSP-32;