The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices.The AD9528 generates six outputs (Output 0 to Output 3, Output 12, and Output 13) with a maximum frequency of 1.25 GHz, and eight outputs with a maximum frequency of up to 1 GHz. Each output can be configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs. The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks.APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B/JESD204C Low jitter, low phase noise clock distribution ATE and high performance instrumentation

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The SC2200 belongs to the 4th-generation family of RF PA linearizers (RFPAL) that provides increased integration and functionality over the previous generations. The device is a dual-path linearizer that is a fully-adaptive, RFIN/RFOUT predistortion linearization solution optimized for a wide range of amplifiers, power levels, and communication protocols. It supports 2G to 4G standards (FDD and TDD) from 698MHz to 2700MHz as well as an expanded range of signal bandwidths from 60MHz down to 1.2MHz. The SC2200 accepts single-ended RF signals to eliminate baluns and features a mirrored pinout facilitating design of both paths. The device uses the PA output and input signals to adaptively generate an optimized correction function to minimize the PA’s distortion. Using RF-domain analog signal processing enables the SC2200 to operate over wide bandwidths and with very low power consumption. The dual linearizer is optimized for high-performance MIMO applications, including small cells, active antenna, and distributed antenna systems.SC2200 and SC1894 RF Power Amplifier Linearizers RF Power Amplifier Linearization Technology ApplicationsAmplifier: Class A/AB, DohertyAverage PA Output Power Examples: Cellular Infrastructure: 27dBm to 40dBmBTS Amplifiers, RRH, Booster Amplifiers, Repeaters, Small Cells, Microcells, Picocells, DAS, AAS and MIMO SystemsCellular InfrastructurePA Process: LDMOS, GaN, HBT, GaAs and InGaPSingle/Multicarrier, Multistandard: CDMA/EVDO, TD-SCDMA, WiMAX, WCDMA/HSDPA, LTE, and TD-LTEWide Range of PAs and Output Power

The AD5110 provides a nonvolatile solution for 128-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W pins. The low resistor tolerance, low nominal temperature coefficient and high bandwidth simplify open-loop applications, as well as tolerance matching applications.The new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 Ω,typical.The wiper settings are controllable through an I2C-compatible digital interface that is also used to readback the wiper register and EEPROM content. Resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy of 0.1%.The AD5110 is available in a 2 mm × 2 mm LFCSP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C.APPLICATIONS Mechanical potentiometer replacement Portable electronics level adjustment Audio volume control Low resolution DAC LCD panel brightness and contrast control Programmable voltage to current conversion Programmable filters, delays, time constants Feedback resistor programmable power supply Sensor calibration

The AD5122/AD5142 potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offeringguaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiringtolerance matching.The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminalsthrough the RAW and RWB string resistors, allowing accurate resistor matching.The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making these devicessuitable for filter design.The low wiper resistance of only 40 Ω at the ends of the resistor array allows for pin to pin connection.The wiper values can be set through an SPI-compatible digital interface that also reads back the wiper register and EEPROMcontents.The AD5122/AD5142 is available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed tooperate over the extended industrial temperature range of −40°C to +125°C. Applications Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies

The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins.The low resistor tolerance and low nominal temperature coefficientsimplify open-loop applications as well as applications requiringtolerance matching.The linear gain setting mode allows independent programmingof the resistance between the digital potentiometer terminals, through the RAW and RWB string resistors, allowing very accurate resistor matching.The high bandwidth and low total harmonic distortion (THD)ensure optimal performance for ac signals, making these devicessuitable for filter design.The low wiper resistance of only 40 Ω at the ends of the resistor array allow for pin-to-pin connection.The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register andEEPROM contents.The AD5124/AD5144/AD5144A are available in a compact, 24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The partsare guaranteed to operate over the extended industrial temperaturerange of −40°C to +125°C.APPLICATIONS Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies

The AD5121/AD5141 potentiometers provide a nonvolatilesolution for 128-/256-position adjustment applications, offeringguaranteed low resistor tolerance errors of ±8% and up to ±6 mAcurrent density in the A, B, and W pins.The low resistor tolerance and low nominal temperature coefficientsimplify open-loop applications as well as applications requiringtolerance matching.The linear gain setting mode allows independent programmingof the resistance between the digital potentiometer terminals,through RAW and RWB string resistors, allowing very accurateresistor matching.The high bandwidth and low total harmonic distortion (THD)ensure optimal performance for ac signals, making it suitablefor filter design.The low wiper resistance of only 40 Ω at the ends of the resistorarray allows for pin-to-pin connection.The wiper values can be set through an SPI-/I2C-compatible digitalinterface that is also used to read back the wiper register andEEPROM contents.The AD5121/AD5141 is available in a compact, 16-lead, 3 mm ×3 mm LFCSP. The devices are guaranteed to operate over theextended industrial temperature range of −40°C to +125°C.APPLICATIONS Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies

The AD5317R, a member of the nanoDAC® family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5317R also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up tozero scale or midscale and remain at that level until a valid writetakes place. Each part contains a per-channel power-downfeature that reduces the current consumption of the device to4 µA at 3 V while in power-down mode.The AD5317R employs a versatile SPI interface that operates atclock rates up to 50 MHz and contains a VLOGIC pin intended for1.8 V/3 V/5 V logic. Product Highlights Precision DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOPApplications Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources

The AD5683R/AD5682R/AD5681R/AD5683, members of thenanoDAC+® family, are low power, single-channel, 16-/14-/12-bitbuffered voltage out digital-to-analog converters (DACs). Thedevices, except the AD5683, include an enabled by default internal2.5 V reference, offering 2 ppm/°C drift. The output span can beprogrammed to be 0 V to VREF or 0 V to 2 × VREF. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The devices are available in a 2.00 mm ×2.00 mm, 8-lead LFCSP or a 10-lead MSOP.The internal power-on reset circuit ensures that the DAC registeris written to zero scale at power-up while the internal outputbuffer is configured in normal mode. TheAD5683R/AD5682R/AD5681R/AD5683 contain a power-downmode that reduces the current consumption of the device to 2 µA(maximum) at 5 V and provides software selectable output loadswhile in power-down mode.The AD5683R/AD5682R/AD5681R/AD5683 use a versatile3-wire serial interface that operates at clock rates of up to 50 MHz.Some devices also include asynchronous RESET pin and VLOGICpin options, allowing 1.8 V compatibilityProduct Highlights High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): ±2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient. 5 ppm/°C maximum temperature coefficient. Two Package Options. 2.00 mm × 2.00 mm, 8-lead LFCSP. 10-lead MSOP.Applications Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources