The AD5424 / AD5433 / AD5445 are CMOS 8-, 10-, and 12-bitcurrent output digital-to-analog converters (DACs), respectively.These devices operate from a 2.5 V to 5.5 V power supply,making them suitable for battery-powered applications andmany other applications. These DACs utilize data readback,allowing the user to read the contents of the DAC register viathe DB pins. On power-up, the internal register and latches arefilled with 0s and the DAC outputs are at zero scale.As a result of manufacturing with a CMOS submicron process,they offer excellent 4-quadrant multiplication characteristics,with large signal multiplying bandwidths of up to 10 MHz.The applied external reference input voltage (VREF) determines thefull-scale output current. An integrated feedback resistor (RFB)provides temperature tracking and full-scale voltage outputwhen combined with an external I-to-V precision amplifier.While these devices are upgrades of the AD5424 / AD5433 /AD5445 in multiplying bandwidth performance, they have alatched interface and cannot be used in transparent mode.The AD5424 is available in a small, 20-lead LFCSP and a small,16-lead TSSOP, while the AD5433 and AD5445 DACs are availablein a small, 20-lead LFCSP and a small, 20-lead TSSOP.The EVAL-AD5445SDZ evaluation board is available forevaluating DAC performance. For more information, see theUG-333 evaluation board user guide.APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming

The AD5532 is a 32-channel, 14-bit voltage-output DAC with an additional infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial interface; VOUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selection is accomplished via Address Bits A0–A4. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD – 2 V because of the headroom of the output amplifier.The device is operated with AVCC = 5 V ± 5%; DVCC = 2.7 V to 5.25 V; VSS = −4.75 V to −16.5 V; and VDD = 8 V to 16.5 V. The AD5532 requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.PRODUCT HIGHLIGHTS 32-channel, 14-bit DAC in one package, guaranteed monotonic. Available in a 74-lead CSPBGA package with a body size of 12 mm ×12 mm. Droopless/infinite sample-and-hold mode.APPLICATIONS Automatic test equipment Optical networks Level setting Instrumentation Industrial control systems Data acquisition Low cost I/O

The AD5541 / AD5542 are single, 16-bit, serial input, voltage output digital-to-analog converters (DACs) that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF.The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of −40°C to +85°C. Offering unbuffered outputs, the AD5541 / AD5542 achieve a 1 μs settling time with low power consumption and low offset errors. Providing a low noise performance of 11.8 nV/√Hz and low glitch, the AD5541 / AD5542 is suitable for deployment across multiple end systems.The AD5542 can be operated in bipolar mode, which generates a ±VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity.The AD5541 / AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. The AD5541 / AD5542 are available in 8-lead and 14-lead SOIC packages.PRODUCT HIGHLIGHTS Single-Supply Operation. The AD5541 and AD5542 are fully specified and guaranteed for a single 2.7 V to 5.5 V supply. Low Power Consumption. These parts consume typically 0.625 mW with a 5 V supply and 0.375 mW at 3 V. 3-Wire Serial Interface. Unbuffered Output Capable of Driving 60 kΩ Loads. This reduces power consumption because there is no internal buffer to drive. Power-On Reset Circuitry.APPLICATIONS Digital gain and offset adjustment Automatic test equipment Data acquisition systems Industrial process control

The AD5541 / AD5542 are single, 16-bit, serial input, voltage output digital-to-analog converters (DACs) that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF.The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of −40°C to +85°C. Offering unbuffered outputs, the AD5541 / AD5542 achieve a 1 μs settling time with low power consumption and low offset errors. Providing a low noise performance of 11.8 nV/√Hz and low glitch, the AD5541 / AD5542 is suitable for deployment across multiple end systems.The AD5542 can be operated in bipolar mode, which generates a ±VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity.The AD5541 / AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. The AD5541 / AD5542 are available in 8-lead and 14-lead SOIC packages.PRODUCT HIGHLIGHTS Single-Supply Operation. The AD5541 and AD5542 are fully specified and guaranteed for a single 2.7 V to 5.5 V supply. Low Power Consumption. These parts consume typically 0.625 mW with a 5 V supply and 0.375 mW at 3 V. 3-Wire Serial Interface. Unbuffered Output Capable of Driving 60 kΩ Loads. This reduces power consumption because there is no internal buffer to drive. Power-On Reset Circuitry.APPLICATIONS Digital gain and offset adjustment Automatic test equipment Data acquisition systems Industrial process control

The AD5544/AD5554 quad, 16-/14-bit, current output, digital-to-analog converters (DACs) are designed to operate from 2.7 V to 5.5 V supply range.The applied external reference input voltage (VREFX) determines the full-scale output current. Integrated feedback resistors (RFB) provide temperature-tracking, full-scale voltage outputs when combined with an external I-to-V precision amplifier.A double-buffered serial data interface offers high speed, 3-wire, SPI- and microcontroller-compatible inputs using serial data in (SDI), a chip select (CS), and clock (CLK) signals. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple packages are used. A common, level-sensitive, load DAC strobe (LDAC) input allows the simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to 0 at system turn-on. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when MSB = 1.The AD5544 is packaged in the compact 28-lead SSOP and 32-lead LFCSP.  The AD5554 is  packaged in the compact 28-lead SSOP.Applications Automatic test equipment Instrumentation Digitally controlled calibration

The AD5544 / AD5554 quad, 16-/14-bit, current output, digital-to-analog converters (DACs) are designed to operate from 2.7 V to 5.5 V supply range.The applied external reference input voltage (VREFx) determines the full-scale output current. Integrated feedback resistors (RFB) provide temperature-tracking, full-scale voltage outputs when combined with an external I-to-V precision amplifier.A double-buffered serial data interface offers high speed, 3-wire, SPI- and microcontroller-compatible inputs using serial data in (SDI), a chip select (CS), and clock (CLK) signals. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple packages are used. A common, level-sensitive, load DAC strobe (LDAC) input allows the simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to 0 at system turn-on. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to half-scale code when MSB = 1.The AD5544 is packaged in the compact 28-lead SSOP and 32-lead LFCSP. The AD5554 is packaged in the compact 28-lead SSOPAPPLICATIONS Automatic test equipment Instrumentation Digitally controlled calibration

CMOS, 12-Bit Serial DACPORT Features: 12-Bit CMOS DAC with On-Chip Voltage Reference Output Amplifier Three Selectable Output Ranges -5 V to + 5 V, 0 V to +5 V, 0 V to +10 V Serial Interface 300 kHz DAC Update Rate Small Size: 16-Lead DIP or SOIC Nonlinearity: ±1/2 LSB Tmin to Tmax Low Power Dissipation: 100 mW Typical  

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

SigmaDSP Compact Digital Audio Processor with Extended Internal Memory Features: Qualified for automotive applications High performance SigmaDSP core enables low latency and audio applications Active Noise Cancellation (ANC) Echo-Canceller and Noise Reduction (ECNR) Surround sound algorithms Features SigmaStudio, a proprietary graphical Integrated Development Environment (IDE), for the development of custom signal flows Comprehensive Toolbox of pre-defined building blocks Faster design time with proven solutions Intuitive system design 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 24 kWords of program memory 80 kWords of parameter/data RAM 6144 SIMD instructions per sample at 48 kHz 1600 ms digital audio delay pool at 48 kHz Audio I/O and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital I/O up to a sample rate of 192 kHz Flexible configuration of I2S, left and right justified, and up to 16-channel TDM formats on serial data pins 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB dynamic range Stereo S/PDIF input and output at 192 kHz Four PDM microphone input channels Multichannel, byte addressable TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor I2C and SPI control interfaces (both slave and master) Standalone operation Self-boot from serial EEPROM 6-channel, 10-bit SAR auxiliary control ADC 14 multipurpose pins for digital controls and outputs On-chip regulator for generating 1.2 V from 1.8 V to 3.3 V supply 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm exposed pad Temperature range: −40°C to +105°C

Three ADCs, One DAC, Low Power Codec with Audio DSPs Features: Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing Tensilica HiFi 3z DSP core Quad MAC per cycle: 24 x 24-bit multiplier and 64-bit accumulator Flexible power operation mode: 24.576 MHz, 49.152 MHz, 73.728 MHz, and 98.304 MHz 336 kB total memory JTAG debug and trace Low latency, 24-bit ADCs and DAC 106 dB SNR (signal through ADC with A-weighted filter) 110 dB combined SNR (signal through DAC and headphone with A-weighted filter) Programmable double precision MAC engine for maximum 24-stage equalizer Serial port sample rates from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 3 differential or single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs Analog differential audio output, configurable as either line output or headphone drive 2 PDM output channels PLL supporting any input clock rate from 30 kHz to 36 MHz 4 channel asynchronous sample rate converters (ASRCs) 2, 16-channel serial audio ports supporting I2S, left justified, right justified, or up to TDM16 (TDM12 in Turbo mode) 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Digital DVDD at 0.85 V to 1.21 V Headphone HPVDD at 1.8 V typical Headphone HPVDD_L at 1.2 V to HPVDD Control/communication interfaces I2C, SPI, or UART control ports Master quad SPI (QSPI) UART communication port Self-boot from QSPI flash Flexible GPIO and IRQ 56-ball, 0.35 mm pitch, 2.980 mm × 2.679 mm WLCSP