12-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches

14-Bit, 210 MSPS TxDAC D/A Converter Features: High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SFDR to Nyquist 83 dBc at 5 MHz output 80 dBc at 10 MHz output 73 dBc at 20 MHz output SNR at 5 MHz output, 125 MSPS: 77 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V reference CMOS-compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages Edge-triggered latches

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

50 V, 130 kHz, 32.5 A, Robust, Over-The-Top Precision Op Amp Features: Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: +3 V to +50 V (to ±25 V for PSRR) Low power supply current: 32.5 μA (typical) Low input offset voltage: ±60 μV maximum Low input offset voltage drift: ±1 μV/°C maximum (B grade) Low input voltage noise 6 Hz typical 1/f noise corner 1000 nV p-p typical at 0.1 Hz to 10 Hz GBP: 130 kHz typical for fTEST = 250 Hz Slew rate: 0.1 V/μs typical at ΔVOUT = 4 V Low power supply current shutdown: 20 μA maximum Low input offset current: ±300 pA maximum Large signal voltage gain: 120 dB minimum for ΔVOUT = 3.5 V CMRR: 120 dB minimum at VCM = −0.1 V to +70 V PSRR: 123 dB minimum at VSY = +3 V to ±25 V Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade) Shutdown feature available for single 6-lead TSOT and dual 10-lead LFCSP packages

50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps Features: Ultrawide common-mode range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: (VSY): +3.15 V to +50 V (±25 V for PSRR) Low supply current: 1.5 mA per channel (typical) Low input offset voltage: ±40 μV maximum Low input offset voltage drift: ±0.4 μV/°C maximum Low voltage noise: 1/f noise corner: 6 Hz typical 150 nV p-p typical at 0.1 Hz to 10 Hz 7 nV/√Hz typical at 100 Hz (en) High speed GBP: 8 MHz typical Slew rate: 5.5 V/μs typical at ΔVOUT = 25 V Low power shutdown: 20 μA maximum Low input bias current: ±10 nA maximum Large signal voltage gain: 120 dB minimum CMRR: 118 dB, minimum PSRR: 123 dB, minimum Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade)

OVP and EMI Protected, Precision, Low Noise and Bias Current Single Op Amp Features: Low offset voltage: 60 μV maximum at 25°C (8-lead and 14-lead SOIC) Low offset voltage drift: 1 μV/°C maximum (8-lead and 14-lead SOIC) Low input bias current: 1 nA maximum at 25°C Low voltage noise density: 8 nV/√Hz typical at 1 kHz Large signal voltage gain (AVO): 100 dB minimum over full supply voltage and operating temperature Input overvoltage protection to 32 V above and below the supply voltage rail Integrated EMI filter 70 dB typical rejection at 1000 MHz 90 dB typical rejection at 2400 MHz Rail-to-rail output swing Low supply current: 500 μA typical per amplifier Wide bandwidth Gain bandwidth product (AV = 100): 3.5 MHz typical Unity-gain crossover (AV = 1): 3.5 MHz typical −3 dB bandwidth (AV = 1): 6 MHz typical Dual-supply operation Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V Unity-gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 2 μV typical Temperature hysteresis: 2 μV typical

30MHz to 1.4GHz IQ Demodulator with IIP2 and DC Offset Control Features: I/Q Bandwidth of 530MHz or Higher High IIP3: 31dBm at 450MHz, 28dBm at 900MHz High IIP2: 70dBm at 450MHz, 65dBm at 900MHz User Adjustable IIP2 to >80dBm User Adjustable DC Offset Null High Input P1dB: 13.1dBm at 900MHz Image Rejection: 45dB at 900MHz Noise Figure: 9.9dB at 450MHz 10dB at 900MHz Conversion Gain: 5.4dB at 450MHz 5.7dB at 900MHz Shutdown Mode Operating Temperature Range (TC): –40°C to 105°C 24-Lead 4mm × 4mm QFN Package

40V, 2.1A Low Dropout Adjustable Linear Regulator with Monitoring and Cable Drop Compensation Features: Wide Input Voltage Range: 1.4V to 40V 1 Resistor Sets Output Voltage: 0.4V to 32V Output Current: 2.1A ±2% Tolerance Over Line, Load and Temperature Output Current Monitor: IMON = IOUT/1000 Temperature Monitor with Programmable Thermal Limit Programmable Cable Drop Compensation Parallel Multiple Devices for Higher Current Dropout Voltage: 330mV 1 Capacitor Soft-Starts Output and Decreases Noise Low Output Noise: 40μVRMS (10Hz to 100kHz) Precision, Programmable External Current Limit Power Good Flag with Programmable Threshold Ceramic Output Capacitors: 10μF Minimum Quiescent Current in Shutdown: <1μA Reverse-Battery, -Current and -Output Protection Available in 5mm × 4mm 16-Lead DFN, 16-Lead TSSOP, 7-Lead DD-Pak and 7-Lead TO-220.LT3086-EP Supports defense and aerospace applications (AQEC standard) Download LT3086-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available on request V62/22602

42V, 2.5A Synchronous Step-Down Regulator with 2.5A Quiescent Current Features: Wide Input Voltage Range: 3.4V to 42V Ultralow Quiescent Current Burst Mode® Operation: 2.5μA IQ Regulating 12VIN to 3.3VOUT Output Ripple < 10mVP-P High Efficiency Synchronous Operation: 96% Efficiency at 1A, 5VOUT from 12VIN 94% Efficiency at 1A, 3.3VOUT from 12VIN Fast Minimum Switch-On Time: 50ns Low Dropout Under All Conditions: 200mV at 1A Allows Use Of Small Inductors Low EMI Adjustable and Synchronizable: 200kHz to 2.2MHz Current Mode Operation Accurate 1V Enable Pin Threshold Internal Compensation Output Soft-Start and Tracking Small Thermally Enhanced 16-Lead MSOP Package AEC-Q100 Qualified for Automotive Applications