Supervisory Circuits Watchdog Supervisor with MR. IC.

Dual 10GHz GBW, 1.1nV/Hz Differential Amplifier/ADC Driver Features: 10GHz Gain-Bandwidth Product 85dB SFDR at 100MHz, 2VP-P 1.1nV/√Hz Input Noise Density Channel Separation 95dB at 100MHz Input Range Includes Ground External Resistors Set Gain (Min 1V/V) 3300V/μs Differential Slew Rate 52mA Supply Current (Per Amplifier) 2.7V to 5.25V Supply Voltage Range Fully Differential Input and Output Adjustable Output Common Mode Voltage Low Power Shutdown Small 20-Lead 4mm × 3mm × 0.75mm LQFN Package

5W AutoResonant Wireless Power Transmitter Features: Monolithic 5W Wireless Power Transmitter AutoResonant™ Switching Frequency Adjusts to Resonant Capacitance and Transmit Coil Inductance* Transmit Power Automatically Adjusts to Receiver Load* Input Voltage Range: 3V to 5.5V Integrated 100mΩ Full Bridge Switches Multiple Foreign Object Detection Methods Programmable Average Input Current Limit and Monitor NTC Input for System/Component Temperature Qualified Power Transfer Wide Operating Switching Frequency Range: 50kHz to 250kHz Thermally Enhanced 4mm × 5mm QFN 20-Lead Package

60V Dual Output Step-Down Controller with Digital Power System Management Features: PMBus/I2C Compliant Serial Interface Telemetry Read-Back Includes VIN, IIN, VOUT, IOUT, Temperature and Faults Programmable Voltage, Current Limit, Digital Soft-Start/Stop, Sequencing, Margining, OV/UV/OC, Frequency, and Control Loop Compensation Output Error Less Than ±0.5% Over Temperature Integrated 16-Bit ADC and 12-Bit DAC Integrated High Side Current Sense Amplifier Internal EEPROM with ECC and Fault Logging Integrated N-Channel MOSFET Gate DriversPower Conversion Wide VIN Range: 5V to 60V VOUT0, VOUT1 Range: 1V to 40V Analog Current Mode Control Accurate PolyPhase® Current Sharing for Up to 6 Phases (85kHz to 500kHz) Available in a 52-Lead (7mm× 8mm) QFN Package

2.5A Supercapacitor Backup Power Manager Features: 2.5A Step-Down Supercapacitor Charger and 2.5A Step-Up Backup Supply 6.5A Switches for 2.5A Backup from One Supercapacitor or Two in Series Input Current Limit Prioritizes Load over Charge Current Input Disconnect Switch Isolates Input During Backup Automatic Seamless Switch-Over to Backup Mode Internal Supercapacitor Balancer (No External Resistors) Programmable Charge Current and Charge Voltage Input Power Fail Indicator System Power Good Indicator Optional OVP Circuitry Protects Device to >60V Constant Frequency Operation Thermally Enhanced 24-Lead 4mm × 5mm QFN Package

25A, Dual PolyPhase Regulator with Digital Power System Management Features: PMBus/I2C Compliant Serial Interface Telemetry Read-Back Includes VIN, IIN, VOUT, IOUT, Temperature and Faults Programmable Voltage, Current Limit, Digital Soft-Start/Stop, Sequencing, Margining, OV/UV/OC Sub-Milliohm DCR Current Sensing Digitally Adjustable Loop Compensation Parameters 0.5% Output Voltage Accuracy Over Temperature Integrated Input Current Sense Amplifier Internal EEPROM with ECC and Fault Logging Integrated N-Channel MOSFET Gate Drivers

CMOS, 12-Bit Serial DACPORT Features: 12-Bit CMOS DAC with On-Chip Voltage Reference Output Amplifier Three Selectable Output Ranges -5 V to + 5 V, 0 V to +5 V, 0 V to +10 V Serial Interface 300 kHz DAC Update Rate Small Size: 16-Lead DIP or SOIC Nonlinearity: ±1/2 LSB Tmin to Tmax Low Power Dissipation: 100 mW Typical  

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch