OVP and EMI Protected, Precision, Low Noise and Bias Current Single Op Amp Features: Low offset voltage: 60 μV maximum at 25°C (8-lead and 14-lead SOIC) Low offset voltage drift: 1 μV/°C maximum (8-lead and 14-lead SOIC) Low input bias current: 1 nA maximum at 25°C Low voltage noise density: 8 nV/√Hz typical at 1 kHz Large signal voltage gain (AVO): 100 dB minimum over full supply voltage and operating temperature Input overvoltage protection to 32 V above and below the supply voltage rail Integrated EMI filter 70 dB typical rejection at 1000 MHz 90 dB typical rejection at 2400 MHz Rail-to-rail output swing Low supply current: 500 μA typical per amplifier Wide bandwidth Gain bandwidth product (AV = 100): 3.5 MHz typical Unity-gain crossover (AV = 1): 3.5 MHz typical −3 dB bandwidth (AV = 1): 6 MHz typical Dual-supply operation Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V Unity-gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 2 μV typical Temperature hysteresis: 2 μV typical

Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier Features: Optimized for ADC synchronization Low power: 22 mW (±12 V supplies) 12 binary gain steps from 1/16 V/V to 128 V/V 3 scaling gains: 1 V/V, 1.25 V/V, and 1.375 V/V ±60 V protected input multiplexer Excellent dc precision Low input offset voltage: ±14 μV maximum Low input offset voltage drift: ±0.08 μV/°C maximum Gain calibration via ROM Low gain drift: ±1 ppm/°C maximum High CMRR: 116 dB minimum, G = 1 V/V Low input bias current: ±1.5 nA maximum High input impedance Integrated input EMI filtering Wide input supply range: ±5 V to ±28 V Dedicated output amplifier supplies 7 GPIO ports with special functions Sequential chip select mode External multiplexer control Excitation current sources SPI port with checksum (CRC) support Internal fault detection Wire break test currents On-chip test multiplexer 28-lead, 5 mm × 5 mm LFCSP, 24-lead TSSOP Specified temperature range: −40°C to +105°C

16-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common range High common-mode rejection Single-ended to differential conversion 2.048 V input range with 4.096 V REFBUF Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball BGA package 4× footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL: 0.4 LSB typical, 1 LSB maximum SINAD: 89 dB typical at 1 kHz THD: 115 dB at 1 kHz, 106 dB at 400 kHz Gain error: 0.005% FS typical Gain error drift: 1 ppm/C maximum On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: 40C to +85C

10 GHz to 40 GHz, 1:4 Channel, 4 Frequency Multiplier/Filter Features: 4 input frequency multiplier with programmable harmonic filter Quad Differential Output PAs with independent Enable Control Input Frequency Range: 2.5 GHz to 10 GHz Output Frequency Range: 10 GHz to 40 GHz Input power: 20 dBm (50 ) Output power: 5 dBm differential (100 ) Harmonic rejection: 20 dBc to 40 dBc at all frequencies 3-Wire or 4-Wire SPI Control of all functions On-Chip Programmable State Machines for fast multiplier/filter and transmitter switching and control On-chip temperature sensor, output power detectors, and ADC DC power: 450 mW (2.5 V supply) 6 mm 6 mm, 40-terminal LGA package

0.5 GHz to 19 GHz Broadband Bi-Directional Single Channel True Time Delay Unit Features:0.5 GHz to 19 GHz frequency rangeProgrammable Time Delay: 7-bit resolutionProgrammable Time Delay ModesTD_Mode0: 0 to 508ps range, 4ps Standard resolutionTD_Mode1: 0 to 254ps range, 2ps High resolutionProgrammable Attenuation: 6-bit resolution31.5 dB adjustment range0.5 dB step sizeFully programmable via a 3-wire or 4-wire SPI interfaceSPI Programmable and Daisy Chaining selectablePower Dissipation: 1 mW with 1.2V and 1.0V Dual Supplies14-pin 2x3mm LFCSP

Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator Features: Fully specified rail-to-rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCC + 0.2 V Low glitch TTL-/CMOS-compatible output stage 40 ns propagation delay Low power 1 mW at 2.5 V Shutdown pin Programmable hysteresis Power supply rejection > 60 dB −40°C to +125°C operation

Microwave Wideband Synthesizer with Integrated VCO Features: Output frequency range: 800 MHz to 12.8 GHz Jitter = 18 fsRMS (Integration BW: 100 Hz to 100 MHz) Jitter = 27 fsRMS (ADC SNR Method) Wideband Noise Floor: -160 dBc/Hz @12 GHz PLL Specifications: -239 dBc/Hz: Normalized In-Band Phase Noise Floor -147 dBc/Hz: Normalized In-Band 1/f Noise Phase Detector Frequency up to 500 MHzReference Input Frequency up to 1 GHz Typical -100 dBc PFD spursReference to Output Delay Specifications: Part-to-Part Standard Deviation: 3 ps Temperature Drift: 0.03 ps/ Adjustment Step Size: <+/-0.1 ps Multi-chip Output Phase Alignment 3.3 V and 5 V Power supplies 7 mm x 7 mm 48 Lead LGA

Low Capacitance, Low Charge Injection, 15 V/+12 V iCMOS Quad SPST Switch Features: 1 pF off capacitance 2.6 pF on capacitance <1 pC charge injection 33 V supply range 120 Ω on resistance Fully specified at ±15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead LFCSP Typical power consumption: <0.03 μW

16-Channel Multiplexer (Superior DG506A Replacement) Features: 44 V Supply Maximum Ratings VSS to VDD Analog Signal Range Single/Dual Supply Specifications Available in 28-Lead DIP, SOIC, PLCC, TSSOP and LCCC Packages Wide Supply Range (10.8 V to 16.5 V) Low Power Dissipation (28 µW max) Low Leakage (20 pA typ) See datasheet for additional features

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier