The ADP5600 is an interleaved charge pump inverter with an integrated, negative, low dropout (LDO) linear regulator. The interleaved charge pump inverter exhibits reduced output voltage ripple and reflected input current noise over conventional inductive or conventional capacitive based solutions. The integrated LDO provides a rail with good regulation at sufficient power supply rejection ratio (PSRR).The ADP5600 charge pump operates via resistor programming or external clock synchronization at switching frequency range of 100 kHz to 1 MHz. Operating at a higher switching frequency allows the use of small input, output, and fly capacitors. To combine the high switching frequency with internal field effect transistors (FETs), compensation, and soft start gives a best-in-class total solution size for negative rail generation.The ADP5600 also features comprehensive fault protection for robust applications. These protections include overload protection, shorted fly capacitor protection, undervoltage lockout (UVLO), and thermal shutdown. For easy sequencing, the ADP5600 has a power-good pin.The integrated LDO of the ADP5600 uses an advanced proprie-tary architecture to provide high power supply rejection. It also achieves decent line and load transient response with only a small 2.2 ?F ceramic output capacitor. The output can be configured via the SEL1 and SEL2 pins to one of four fixed output voltages and is adjustable from ?0.505 V to ?VIN + 0.5 V via an external feedback divider.APPLICATIONSPowering the negative rail on bipolar/split supply ADC/DAC/AMP/mux applications

The ADP7102 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 ?F ceramic output capacitor. The ADP7102 is available in seven fixed output voltage options and an adjustable version, which allows output voltages that range from 1.22 V to VIN ? VDO via an external feedback divider. The ADP7102 output noise voltage is 15 ?V rms and is independent of the output voltage. A digital power good output allows power system monitors to check the health of the output voltage. A user programmable precision undervoltage lockout function facilitates sequencing of multiple power supplies. The ADP7102 is available in 8-lead, 3 mm ? 3 mm LFCSP and 8-lead SOIC packages. The LFCSP offers a very compact solution and also provides excellent thermal performance for applications requiring up to 300 mA of output current in a small, low-profile footprint. APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation

The ADP7159 is an adjustable linear regulator that operates from 2.3 V to 5.5 V and provides up to 2 A of output current. Output voltages from 1.2 V to 3.3 V are possible depending on the model. Using an advanced proprietary architecture, the device provides high power supply rejection and ultralow noise, achieving excellentline and load transient response with only a 10 ?F ceramicoutput capacitor.The ADP7159 is available in four models that optimize powerdissipation and PSRR performance as a function of the inputand output voltage. The typical output noise of the ADP7159 regulator is 0.9 ?V rmsfrom 100 Hz to 100 kHz and 1.7 nV/?Hz for noise spectral densityfrom 10 kHz to 1 MHz. The ADP7159 is available in 10-lead,3 mm ? 3 mm LFCSP and 8-lead SOIC packages, making it notonly a very compact solution, but also providing excellent thermal performance for applications requiring up to 2 A of outputcurrent in a small, low profile footprint.Applications Regulation to noise sensitive applications: phase-locked loops (PLLs), voltage controlled oscillators (VCOs), and PLLs with integrated VCOs Communications and infrastructure Backhaul and microwave links

The ADRF5021 is a general-purpose single-pole, double-throw (SPDT) switch manufactured using a silicon process. It comes in a 3 mm ? 3 mm, 20-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 9 kHz to 30 GHz.This broadband switch requires dual supply voltages, +3.3 V and ?2.5 V, and provides CMOS/LVTTL logic-compatible control.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, electronic counter measures (ECMs) Broadband telecommunications systems

The ADRF5024 is a reflective, single-pole double-throw (SPDT) switch manufactured in the silicon process.This switch operates from 100 MHz to 44 GHz with better than 1.7 dB of insertion loss and 35 dB of isolation. The ADRF5024 has an radio frequency (RF) input power handling capability of 27 dBm for both the through path and hot switching.The ADRF5024 draws a low current of 14 ?A on the positive supply of +3.3 V and 120 ?A on negative supply of ?3.3 V. The device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)compatible controls.The ADRF5024 is pin-compatible with the ADRF5025, low frequency cutoff version, which operates from 9 kHz to 44 GHz.The ADRF5024 RF ports are designed to match a characteristic impedance of 50 ?. For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the Electrical Specifications section, Typical Performance Characteristics section, and Applications Information section for more details.The ADRF5024 comes in a 2.25 mm ? 2.25 mm, 12-terminal, RoHS-compliant, land grid array (LGA) package and can operate between ?40?C to +105?C.The ADRF5024-EP supports defense and aerospace applications (AQEC).Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5043 is a nonreflective, SP4T switch manufactured in the silicon on insulator (SOI) process.The ADRF5043 operates from 9 kHz to 44 GHz with an insertion loss of lower than 2.5 dB and an isolation of higher than 36 dB. The device has a RF input power handling capability of 24 dBm for both through and terminated paths.The ADRF5043 requires a dual-supply voltage of +3.3 V and ?3.3 V. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5043 has enable and logic select controls to feature all off state and port mirroring, respectively. The ADRF5043 is pin compatible with the ADRF5042 fast switching version, which operates from 100 MHz to 44 GHz.The ADRF5043 comes in a 24-terminal, 3 mm ? 3 mm, RoHS compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.Applications Industrial Scanners Test instrumentation Cellular infrastructure?millimeterwave (mmWave) 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5044 is a general-purpose, single-pole, four-throw (SP4T) switch manufactured using a silicon process. It comes in a 24-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 100 MHz to 30 GHz.This broadband switch requires dual-supply voltages, +3.3 V and ?3.3 V, and provides complementary metal-oxide semiconductor (CMOS)/low voltage transistor-transistor logic (LVTTL) logic-compatible control.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems

The ADRF6821 is a highly integrated, dual radio frequency (RF) input, zero intermediate frequency (IF)/low IF RFIC receiverwith a quadrature demodulator, digital step attenuator (DSA),IF linear amplifiers, an integrated, fractional-N phase-locked loop (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication digital predistortion (DPD) systems.The high isolation 2:1 RF switch and on-chip wideband RFbalun enable the ADRF6821 to support two single-ended, 50 ? terminated RF inputs. A programmable attenuator ensures anoptimal differential RF input level to the high linearity demodulatorcore. The integrated attenuator offers an attenuation range of 15 dB with a step size of 1 dB. High linearity IF amplifiers follow the demodulator and provide an interface to the next componentin the chain, typically an analog-to-digital converter (ADC).The ADRF6821 offers two alternatives for generating thedifferential local oscillator (LO) input signal: internally viathe on-chip fractional-N synthesizer with low phase noiseVCOs or externally via a low phase noise LO signal. Theintegrated synthesizer enables continuous LO coverage from 450 MHz to 2800 MHz. The PLL reference input supports awide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).When selected, the output of the internal fractional-N synthesizeris applied to a divide by 2, quadrature phase splitter. From theexternal LO path, a 2? LO signal can be used with the divide by 2,quadrature phase splitter to generate the quadrature LO inputs to the mixers.The ADRF6821 is fabricated using an advanced silicon germanium(SiGe), bipolar complementary metal oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS compliant,8 mm ? 8 mm LFCSP package with an exposed pad. Performanceis specified over the ?40?C to +105?C case temperature range.Applications Cellular W-CDMA/GSM/LTE DPD receivers? Microwave, point to point radios

The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual channel transmitters, observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 2G, 3G and 4G macro-cell base stations, and active antenna, applications.The transmitters use an innovative direct conversion modulator that achieves multi-carrier macro-base-station quality performance and very low power. In 3G/4G mode, the maximum large-signal bandwidth is 200MHz. In MC-GSM mode, which has higher in-band SFDR, the maximum large-signal bandwidth is 75MHz.The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated. The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer is used to generate the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All VCO and loop filter components are integrated.The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode. The core of the ADRV9008-2 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment