The AD8305 is an inexpensive microminiature logarithmic converter optimized for determining optical power in fiber optic systems. It uses an advanced implementation of a classic translinear (junction based) technique to provide a large dynamic range in a versatile and easily used form. A single-supply voltage of between 3 V and 12 V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 mA) permits use in battery-operated applications.The input current, IPD, of 10 nA to 1 mA applied to the INPT pin is the collector current of an optimally scaled NPN transistor, which converts this current to a voltage (VBE) with a precise logarithmic relationship. A second such converter is used to handle the reference current (IREF) applied to pin IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The output of the logarithmic front end is available at Pin VLOG.The basic logarithmic slope at this output is nominally 200 mV/decade (10 mV/dB). Thus, a 100 dB range corresponds to an output change of 1 V. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the AD8305 voltage reference output of 2.5 V at Pin VREF can be used to improve the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), AD7823 (serial 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of the logarithmic slope can be provided using a simple external resistor network.The logarithmic intercept (also known as the reference current) is nominally positioned at 1 nA by the use of the externally generated current, IREF, of 10 μA, provided by a 200 kΩ resistor connected between VREF, at 2.5 V, and the reference input, IREF, at 0.5 V. The intercept can be adjusted over a wide range by varying this resistor. The AD8305 can also operate in a log ratio mode, with the numerator current applied to INPT and the denominator current applied to IREF.A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of 10 mV/dB to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current sourcing capacity is 25 mA.It is a fundamental aspect of translinear logarithmic converters that the small signal bandwidth falls as the current level diminishes, and the low frequency noise-spectral density increases. At the 10 nA level, the bandwidth of the AD8305 is about 50 kHz and increases in proportion to IPD up to a maximum value of about 15 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize lowpass filters of up to three poles.The AD8305 is available in a 16-lead LFCSP package and is specified for operation from −40°C to +85°C.Applications  Optical power measurement Wide range baseband logarithmic compression Measurement of current and voltage ratios Optical absorbance measurement

INSTRUMENT AMPLIFIER;

24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 5 SPS to 250 kSPS Performance specifications 17.2 noise free bits at 250 kSPS 20.2 noise free bits at 2.5 kSPS 24 noise free bits at 20 SPS INL: ±1 ppm of FSR 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 8 fully differential channels or 16 single-ended channels Crosspoint multiplexer Channel scan data rate of 50 kSPS/channel (20 ìs settling) On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2 V to 5 V (nominal) Split supply with AVDD1/AVSS at ±2.5 V ADC current: 8.4 mA Temperature range: −40°C to +105°C 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) Serial port interface (SPI), QSPI, MICROWIRE, and DSP compatible

The fourth generation of SHARC® Processors now includes the low power floating point DSP products – the ADSP-21478 and ADSP-21479 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting a single chip solution. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.The ADSP-21478 offers a very low power and high performance – 266 MHz/1596 MFLOPs – in a BGA and LQFP package within the fourth generation SHARC Processor family. This feature of power makes the ADSP-21478 particularly well suited to address the automotive audio and many industrial control segments where low power is a requirement. In addition to its high core performance, the ADSP-21478 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The ADM1186-1 and ADM1186-2 are integrated, four-channel, voltage monitoring and sequencing devices. A 2.7 V to 5.5 V power supply is required on the VCC pin for power.Four precision comparators monitor four voltage rails, with all comparators sharing a 0.6 V reference and a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the Under Voltage (UV) trip points for the monitored supply rails.The ADM1186-1 and ADM1186-2 have four open drain enable outputs, OUTx, that are used to enable power supplies. An open drain power good output, PWRGD, is provided that indicatesthe four VINx inputs are above their UV thresholds.A state machine monitors the state of the UP and?DOWN pins on the ADM1186-1 or the UP/overbar: DOWN pin on the ADM1186-2 to control the supply sequencing direction. In the ?Wait Start?state, a rising edge transition on the UP or UP/DOWN pin triggers a power-up sequence. A falling edge transition on the DOWN or UP/DOWN pin in the ?Power Up Done? statetriggers a power down sequence.During a power up sequence, the state machine enables each power supply in turn. The supply output voltage is monitored to determine if it rises above the UV threshold level within a userdefined duration called the blanking time. If a supply rises above the UV threshold then the next enable output in the sequence is turned on. In addition to the blanking time a user may also define sequencing time delays between each enable output turning on. When all four enable outputs are on, and the four VINx pins are above their UV trip points the power up sequence is complete. The ADM1186-1 provides an open drain pin, SEQ_DONE, that is asserted high to provide an indication that an up sequence is complete. The SEQ_DONE pins is allows multiple cascadedADM1186-1 devices to be perform controlled power up and down sequences. During a power down sequence the enable outputs turn off inreverse order. The sequence time delays between successive supplies the same as during the power up sequence, and no blanking time is used during a power down sequence. At the end of a down sequence the SEQ_DONE pin is brought low. During sequencing and when powered up, the state machine continuously monitors for any fault conditions. Faults include a UV condition on any of the inputs, or an unexpected controlinput. Any fault that occurs causes the state machine to enter a fault handler. This immediately turns off all enable outputs, and ensures that the device is ready to start a new up sequence. The ADM1186-1 has a bi-directional open drain pin, FAULT, that facilitates fault handling when using multiple devices. An ADM1186-1 experiencing a fault condition drives the FAULT pin low, causing other connected ADM1186-1devices to enter their own fault handling state.The ADM1186-1 is available in a 20-lead QSOP package andthe ADM1186-2 is available in a 16-lead QSOP package.

Precision Instrumentation Amplifier

SHARC DIGITAL SIGNAL PROCESSORS;

ADC, 14-BIT, 105MSPS, LFCSP-48 ROHS COMPLIANT: YES

The ADP2443 is synchronous step-down, dc-to-dc regulator with an integrated 98 m?, high-side power metal oxide semicon-ductor field effect transistor (MOSFET) and a 35 m?, synchronous rectifier MOSFET to provide a high efficiency solution in a compact 4 mm ? 4 mm LFCSP package. The regulators operate from an input voltage range of 4.5 V to 36 V. The output voltage can be adjusted down to 0.6 V and deliver up to 3 A of continuous current. The fast 50 ns minimum on time allows the regulators convert high input voltage to low output voltage at high frequency.The ADP2443 uses an emulated current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. The switching frequency of the ADP2443 can be programmed from 200 kHz to 1.8 MHz. The synchronization function allows the switching frequency be syn-chronized with an external clock to minimize the system noise.The ADP2443 targets high performance applications that require high efficiency and design flexibility. External compensation and an adjustable soft start function provide design flexibility. The power-good output and precision enable input provide simple and reliable power sequencing.Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), short-circuit protection (SCP), and thermal shutdown (TSD).The ADP2443 operates over the ?40?C to +125?C operating junction temperature range and is available in a 24-lead, 4 mm ? 4 mm LFCSP package.Applications Intermediate power rail conversion Multicell battery powered systems Process control and industrial automation Healthcare and medical Networking and servers

HALL EFFECT SENSOR ROHS COMPLIANT: YES