25A, Dual PolyPhase Regulator with Digital Power System Management Features: PMBus/I2C Compliant Serial Interface Telemetry Read-Back Includes VIN, IIN, VOUT, IOUT, Temperature and Faults Programmable Voltage, Current Limit, Digital Soft-Start/Stop, Sequencing, Margining, OV/UV/OC Sub-Milliohm DCR Current Sensing Digitally Adjustable Loop Compensation Parameters 0.5% Output Voltage Accuracy Over Temperature Integrated Input Current Sense Amplifier Internal EEPROM with ECC and Fault Logging Integrated N-Channel MOSFET Gate Drivers

3GHz to 20GHz Microwave Mixer with Wideband DC to 6GHz IF Features:Integrated LO Buffer: 0dBm LO Drive50 Wideband Matched RF and LO PortsWide IF Bandwidth: DC to 6GHzUpconversion or DownconversionHigh IIP3:+22.5dBm at 10GHz+18.3dBm at 17GHz+14.6dBm Input P1dB at 10GHz8dB Conversion Loss at 10GHz3.3V/132mA SupplyFast Turn ON/OFF for TDD Operation3mm × 2mm, 12-Lead QFN Package

Very Low Noise, Low Distortion Active RC Quad Universal Filter Features: Continuous Time—No Clock Four 2nd Order Filter Sections, 20kHz to 300kHz Center Frequency Butterworth, Chebyshev, Elliptic or Equiripple Delay Response Lowpass, Bandpass, Highpass Responses 99dB Typical S/N, ±5V Supply (Q = 1) 93dB Typical S/N, Single 5V Supply (Q = 1) Rail-to-Rail Input and Output Voltages DC Accurate to 3mV (Typ) ±0.5% Typical Center Frequency Accuracy “Zero-Power” Shutdown Mode Single or Dual Supply, 5V to 10V Total Resistor-Programmable fO, Q, Gain

High Voltage, Latch-Up Proof, 16-Channel Multiplexer Features: Latch-up proof 3.5 pF off source capacitance 64 pF off drain capacitance 0.35 pC typical charge injection ±0.02 nA on channel leakage Low on resistance: 155 typical ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation VSS to VDD analog signal range Human body model (HBM) ESD rating - 8 kV all other pins

Dual Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 16 MUPS single channel rate in fast mode 11 MUPS single channel rate in precision mode 78 ns small signal settling time to 0.1% accuracy 100 ns large signal settling time to 0.1% accuracy Ultrasmall glitch: <50 pV×s Ultralow latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic) and dual SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient Small package: 4 mm × 4 mm LFCSP

Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 33 MUPS single channel rate in fast mode 22 MUPS single channel rate in precision mode 65 ns small signal settling time to 0.1% accuracy 100ns large signal settling time to 0.1% accuracy Ultra small glitch: < 50 pV×s Ultra low latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic), dual, and quad SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient 5 mm × 5 mm LFCSP

16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit, no missing codes SNR: 96.2 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −99 dB at fIN = 100 kHz SINAD: 88.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 99.3 dB for OSR = 2 126 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Features: Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥79% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Pseudo differential analog input range 0 V to VREF with VREF from 2.4 V to 5.1 V Throughput: 2 MSPS/1 MSPS/500 kSPS options INL: ±3.2 LSB maximum Guaranteed 18-bit, no missing codes SNR: 95 dB at fIN = 1 kHz at VREF = 5 V THD: −125 dB at fIN = 1 kHz, −108 dB at fIN = 100 kHz SINAD: 84.5 dB at fIN = 1 MHz (see Figure 17 in data sheet) Oversampled dynamic range 98 dB for OSR = 2 125 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.5 mW at 500 kSPS (VDD only) 70 μW at 10 kSPS, 14 mW at 2 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C

Single Supply, 24-Bit, Sigma-Delta ADC with 10 V and 0 mA to 20 mA Inputs Features: Internal or external clock Tested for robustness per: IEC61000-4-2, IEC61000-4-3, IEC61000-4-4, IEC61000-4-5, IEC61000-4-6, CISPR 11 24-bit ADC with integrated analog front end Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 μs settling) 16 noise free bits at 1 kSPS per channel 85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, 4 differential or 8 single-ended Pin absolute maximum rating ±50 V Absolute input pin voltage up to ±20 V ≥1 MΩ impedance ±0.06% accuracy at 25°C 0 mA to 20 mA inputs, 4 single-ended Pin absolute maximum rating ±50 mA Input range from −0.5 mA to +24 mA 60 Ω impedance ±0.08% accuracy at 25°C On-chip 2.5 V reference ±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total IDD = 3.9 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible

16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC Features: Easy Drive Reduced analog input and reference drive requirements On-chip reference buffer (WLCSP only) Overvoltage protection up to 5 mA on each analog input Long acquisition phase, ≥71.5% (715 ns/1000 ns) of cycle time at 1 MSPS High performance Sample rate: 500 kSPS (AD4695) or 1 MSPS (AD4696) INL: ±1.0 LSB maximum Guaranteed 16-bit, no missing codes SINAD: 93 dB typical, fIN = 1 kHz Oversampled dynamic range: 111.2 dB, OSR = 64 Small footprint, high channel density 32-lead 5 mm × 5 mm LFCSP 36-ball 2.96 mm × 2.96 mm WLCSP Easy Drive features support system level designs with fewer components Enhanced digital functionality First conversion accurate, no latency or pipeline delay Fast conversion time and dual-/quad-SDO modes allow low SPI clock rates Customizable channel sequencer On-chip oversampling and decimation Threshold detection alerts Offset and gain correction Autonomous conversion (autocycle) mode 1.14 V to 1.98 V logic SPI Low power 8 mW at fS = 1 MSPS and 4 mW at fS = 500 kSPS 4 μW standby power dissipation with the internal LDO disabled Internal LDO enables 3.15 V to 5.5 V, single analog supply operation Wide operating temperature range: −40°C to +125°C