The AD5593R has eight input/output (I/O) pins, which can beindependently configured as digital-to-analog converter (DAC)outputs, analog-to-digital converter (ADC) inputs, digital outputs,or digital inputs. When an I/O pin is configured as an analogoutput, it is driven by a 12-bit DAC. The output range of theDAC is 0 V to VREF or 0 V to 2 ? VREF. When an I/O pin isconfigured as an analog input, it is connected to a 12-bit ADCvia an analog multiplexer. The input range of the ADC is 0 V toVREF or 0 V to 2 ? VREF. The I/O pins can also be configured tobe general-purpose, digital input or output (GPIO) pins. Thestate of the GPIO pins can be set or read back by accessing theGPIO write data register and GPIO read configuration registers,respectively, via an I2C write or read operation.The AD5593R has an integrated 2.5 V, 20 ppm/?C reference thatis turned off by default and an integrated temperature indicatorthat gives an indication of the die temperature. The temperaturevalue is read back as part of an ADC read sequence.The AD5593R is available in 16-lead TSSOP and LFCSP, as wellas a 16-ball WLCSP, and operates over a temperature range of?40?C to +105?C.Applications Control and monitoring General-purpose analog and digital I/O

Demonstration circuit 2779A is an 8V, 16A synchronous step-down Silent Switcher® 2 with spread spectrum frequency modulation featuring the LT8644S. The demo board is designed for 1.2V output from a 2.7V to 8V input. The LT8644S is a compact, ultralow emission, high efficiency, and high speed synchronous monolithic stepdown switching regulator. The integrated bypass capacitors optimize all the fast current loops and make it easier to minimize EMI emissions by reducing layout sensitivity. Selectable spread spectrum mode further improves EMI performance, making it perfect solution to the noise sensitive applications. Peak current mode control with minimum on-time of as low as 20ns allows high step-down conversion even at high frequency. The LT8644S switching frequency can be programmed either via an external resistor or an external clock over a 300kHz to 3.5MHz range. The default frequency of demo circuit 2779A is 2MHz. The SYNC/MODE pin on the demo board DC2779A is grounded (JP1 at BURST position) by default for low ripple Burst Mode® operation. It can be configured into different operation modes through JP1 and SYNC terminal (Table 1 in the demo manual). Figure 4 in the demo manual shows the efficiency of the circuit at 3.3V input and 5V input in force continuous mode operation (input from VIN terminal). To get accurate efficiency measurement, measure the input voltage at the VIN_SENSE/GND terminals and measure the output voltage at the VOUT+ SENSE/VOUT– SENSE terminals. Figure 5 shows the LT8644S temperature rise on DC2779A demo board at 3.3V input and 5V input in forced continuous mode. The LT8644S is assembled in a 4mm × 4mm LQFN package with exposed pads for low thermal resistance. The rated maximum continuous load current is 16A, while derating may be necessary for certain input voltage and thermal conditions. The demo board has an EMI filter installed. This EMI filter can be included by applying the input voltage at the VEMI terminal. The EMI performance of the board (with EMI filter) is shown on Figure 6 in the demo manual. The red lines in EMI Performance are CISPR25 Class 5 limits. The figure shows that the LT8644S circuit passes the test with a wide margin. To achieve EMI performance as shown in Figure 6, the input EMI filter is required and the input voltage should be applied to VEMI terminal, and the test setup can be referred to the CISPR25 standards. If the input is applied to VIN terminal, the EMI filter is bypassed. The LT8644S data sheet gives a complete description of the part, the operation and application information. The data sheet must be read in conjunction with the demo manual for demo circuit 2779A. The layout recommendations for low EMI operation and maximum thermal performance are available in the data sheet section Low EMI PCB Layout and Thermal Considerations. Contact ADI applications engineer for support.

The LTC5584 is a direct conversion quadrature demodulator optimized for high linearity receiver applications in the 30MHz to 1.4GHz frequency range. It is also usable in the 10MHz to 30MHz and 1.4GHz to 2GHz ranges with reduced performance. It is suitable for communications receivers where an RF signal is directly converted into I and Q baseband signals with bandwidth of 530MHz or higher. The LTC5584 incorporates balanced I and Q mixers, LO buffer amplifiers and a precision, high frequency quadrature phase shifter. In addition, the LTC5584 provides four analog control voltage interface pins for IIP2 and DC offset correction, greatly simplifying system calibration.The high linearity of the LTC5584 provides excellent spurfree dynamic range for the receiver. This direct conversion demodulator can eliminate the need for intermediate frequency (IF) signal processing, as well as the corresponding requirements for image filtering and IF filtering. These I/Q outputs can interface directly to channel-select filters (LPFs) or to baseband amplifiers.Applications LTE/W-CDMA/TD-SCDMA Base Station Receivers Wideband DPD Receivers Point-To-Point Broadband Radios High Linearity Direct Conversion I/Q Receivers Image Rejection Receivers

3kV rms, Default Low, Dual-Channel Digital Isolators (2/0 Channel Directionality) Features: Up to 100 Mbps data rate (NRZ) Low propagation delay: 23 ns typical Low dynamic power consumption Bidirectional communication 3.3 V to 5 V level translation High temperature operation: 125°C High common-mode transient immunity: >25 kV/μs Default high output: ADuM1280/ADuM1281 Default low output: ADuM1285/ADuM1286 Narrow body, RoHS-compliant, 8-lead SOIC Safety and regulatory approvals UL recognition: 3000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak Qualified for automotive applications

OTHER MPUS MICROPROCESSORS;

The LTC2631 is a family of 12-, 10-, and 8-bit voltage-output DACs with an integrated, high accuracy, low-drift reference in an 8-lead TSOT-23 package. It has a rail-to-rail output buffer that is guaranteed monotonic.The LTC2631-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2631-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. A 10ppm/?C reference output is available at the REF pin.Each DAC can also operate in External Reference mode, in which a voltage supplied to the REF pin sets the fullscale output.The LTC2631 DACs use a 2-wire, I2C-compatible serial interface. The LTC2631 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz).The LTC2631 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale after power-up.Applications Mobile Communications Process Control and Industrial Automation Automatic Test Equipment Portable Equipment Automotive Optical Networking

The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).ANALOG INTERFACEThe AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 × 1024 at 75 Hz).The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications.DIGITAL INTERFACEThe AD9880 contains a HDMI v1.1 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.1 protocol.Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount Pb-free plastic package and is specified over the 0 ºC to 70 ºC temperature range.APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with <600 ps resolution.The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS 12-bit A/D converter. The timing driver provides the high speed CCD clock drivers for RG and H1–H4. Operation is programmed using a 3-wire serial interface.Packaged in a space-saving 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of –2ºC to +8ºC.APPLICATIONS Digital still cameras High speed digital imaging applications

The AD7124-8 is a low power, low noise, completely integratedanalog front end for high precision measurement applications.The device contains a low noise, 24-bit Σ-Δ analog-to-digitalconverter (ADC), and can be configured to have 8 differentialinputs or 15 single-ended or pseudo differential inputs. The onchiplow gain stage ensures that signals of small amplitude canbe interfaced directly to the ADC.One of the major advantages of the AD7124-8 is that it gives theuser the flexibility to employ one of three integrated powermodes. The current consumption, range of output data rates,and rms noise can be tailored with the power mode selected.The device also offers a multitude of filter options, ensuring thatthe user has the highest degree of flexibility.The AD7124-8 can achieve simultaneous 50 Hz and 60 Hzrejection when operating at an output data rate of 25 SPS (singlecycle settling), with rejection in excess of 80 dB achieved at loweroutput data rates.The AD7124-8 establishes the highest degree of signal chainintegration. The device contains a precision, low noise, lowdrift internal band gap reference and accepts an externaldifferential reference, which can be internally buffered. Otherkey integrated features include programmable low drift excitationcurrent sources, burnout currents, and a bias voltage generator,which sets the common-mode voltage of a channel to AVDD/2.The low-side power switch enables the user to power downbridge sensors between conversions, ensuring the absoluteminimal power consumption of the system. The device alsoallows the user the option of operating with either an internalclock or an external clock.The integrated channel sequencer allows several channels to beenabled simultaneously, and the AD7124-8 sequentially convertson each enabled channel, simplifying communication with thedevice. As many as 16 channels can be enabled at any time, achannel being defined as an analog input or a diagnostic suchas a power supply check or a reference check. This uniquefeature allows diagnostics to be interleaved with conversions.The AD7124-8 also supports per channel configuration. Thedevice allows eight configurations or setups. Each configurationconsists of gain, filter type, output data rate, buffering, andreference source. The user can assign any of these setups on achannel by channel basis.The AD7124-8 also has extensive diagnostic functionalityintegrated as part of its comprehensive feature set. Thesediagnostics include a cyclic redundancy check (CRC), signalchain checks, and serial interface checks, which lead to a morerobust solution. These diagnostics reduce the need for externalcomponents to implement diagnostics, resulting in reducedboard space needs, reduced design cycle times, and cost savings.The failure modes effects and diagnostic analysis (FMEDA) of atypical application has shown a safe failure fraction (SFF) greaterthan 90% according to IEC 61508.The device operates with a single analog power supply from 2.7 Vto 3.6 V or a dual 1.8 V power supply. The digital supply has arange of 1.65 V to 3.6 V. It is specified for a temperature rangeof −40°C to +125°C. The AD7124-8 is housed in a 32-leadLFCSP package.Note that, throughout this data sheet, multifunction pins, suchas DOUT/RDY, are referred to either by the entire pin name orby a single function of the pin, for example, RDY, when onlythat function is relevant.Applications Temperature measurement Pressure measurement Industrial process control Instrumentation Smart transmitters

The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver.The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output.The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition.The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807.The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance.The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater.Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency.The AD807 consumes 140 mW and operates from a single power supply at either +5 V or –5.2 V.