28 V, 200 mA, Low Noise, Linear Regulator Features: Low noise: 18 μV rms Power supply rejection ratio (PSRR): 66 dB at 10 kHz at VOUT = −3 V Positive or negative enable logic Stable with small 2.2 μF ceramic output capacitor Input voltage range: −2.7 V to −28 V Maximum output current: −200 mA Low dropout voltage: −185 mV at −200 mA load Initial accuracy: ±1% Accuracy over line, load, and temperature +2% maximum/−3% minimum Low quiescent current, IGND = −650 μA with −200 mA load Low shutdown current: −2 μA Adjustable output from −1.22 V to −VIN + VDO Current-limit and thermal overload protection 6- and 8-lead LFCSP and 5-lead TSOT Supported by ADIsimPower tool

5.9 GHz to 23.6 GHz, Wideband, Microwave Upconverter Features: Wideband RF output frequency range: 5.9 GHz to 23.6 GHz Two upconversion modes Direct conversion from baseband I/Q to RF Single sideband upconversion from real IF LO input frequency range: 5.4 GHz to 14 GHz LO doubler for up to 28 GHz Matched 100 Ω balanced RF output, LO input, and IF input High impedance baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator and power detector for Tx power control Programmable via 4-wire SPI interface 32-lead, 5 mm × 5 mm LFCSP microwave packaging

Integrated Dual RF Receiver Features: Dual receivers Maximum Receiver BW: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuneable range: 75 MHz to 6000 MHz

Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with 10 V Inputs Features:24-bit ADC with integrated AFEFast and flexible output rate: 2.5 SPS to 125 kSPSChannel scan data rate of 24,845 SPS per channel (40.25 s settling)85 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel10 V inputs, either 8 differential or 16 single-endedVIN pin absolute maximum rating 65 VAbsolute input pin voltage up to 20 VMinimum 1 M impedanceOn-chip 2.5 V reference0.12% initial accuracy at 25C, 5 ppm/C (typical) driftInternal or external clockPower suppliesAVDD = 4.5 V to 5.5 VIOVDD = 2 V to 5.5 VTotal current consumption AVDD + IOVDD (IDD) = 10.4 mATemperature range: 40C to +105C3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)SPI, QSPI, MICROWIRE, and DSP compatible

32 A, Ultra Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO Features: Ultralow current consumption (typical): 32 μA: continuous conversion mode (gain = 128) 5 μA: duty cycling mode (ratio = 1/16) 0.5 μA: standby mode 0.1 μA: power-down mode Built-in features for system level power savings: Current saving duty cycle ratio: 1/4 or 1/16 Smart sequencer and per channel configuration minimizes host processor load Deep embedded FIFO minimizes host processor load (depth of 256 samples) Autonomous FIFO interrupt functionality, threshold detection Single supply as low as 1.71 V increasing battery length RMS noise: 25 nV rms at 1.17 SPS (gain = 128) – 48 nV/√Hz Up to 22 noise free bits (gain = 1) Output data rate: 1.17 SPS to 2.4 kSPS Operates from 1.71 V to 3.6 V single supply or ±1.8 V split supplies Band gap reference with 15 ppm/°C maximum drift PGA with rail-to-rail analog input Adaptable sensor interfacing functionality: Matched programmable excitation currents for RTDs On-chip bias voltage generator for thermocouples Low-side power switch for bridge transducers Sensor open wire detection Internal temperature sensor and oscillator Self and system calibration Flexible filter options Simultaneous 50 Hz/60 Hz rejection (on selected filter options) General-purpose outputs Diagnostic functionality Crosspoint multiplexed inputs 8 differential/16 pseudo differential inputs 5 MHz SPI (3-wire or 4-wire) Available in 35-ball, 2.74 mm × 3.6 mm WLCSP Temperature range: −40°C to +105°C

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

GaAs, pHEMT, Low Noise Amplifier, 20 GHz to 54 GHz Features: Gain: 21.5 dB typical at 30 GHz to 44 GHz Input return loss: 22 dB typical at 30 GHz to 44 GHz Output return loss: 23 dB typical at 30 GHz to 44 GHz OP1dB: 14 dB typical at 30 GHz to 44 GHz PSAT: 18 dBm typical at 30 GHz to 44 GHz OIP3: 21.5 dBm typical at 30 GHz to 44 GHz Noise figure: 3.0 dB typical at 30 GHz to 44 GHz 3 V supply voltage at 120 mA 50 Ω matched input and output Die size: 2.3 mm x 1.45 mm x 0.1 mm

2 GHz to 28 GHz, GaAs, pHEMT, MMIC Low Noise Amplifier Features: P1dB: 20 dBm typical at 2 GHz to 6 GHz PSAT: 20.5 dBm typical at 2 GHz to 6 GHz Gain: 15.5 dB typical at 6 GHz to 28 GHz Noise figure: 2.5 dB typical at 2 GHz to 20 GHz OIP3: 26 dBm typical at 2 GHz to 6 GHz Supply voltage: 5 V at 53 mA 50 Ω matched input and output ADL9006CHIPS P1dB: 19 dBm typical at 2 GHz to 14 GHz Gain: 15.5 dB typical at 14 GHz to 22 GHz Noise figure: 2.2 dB at 2 GHz to 14 GHz Output IP3: 24 dBm typical at 2 GHz to 14 GHz Power supply voltage: 5 V with a 55 mA total supply current 50 Ω matched input and output

Low Power, +5V CMOS RS-232 100kBPS Transceiver with 2 Drivers/Receivers Features: Single 5 V Power Supply  Meets All EIA-232-E and V.28 Specifications  120 kB/s Data Rate  On-Board DC-DC Converters  ±9 V Output Swing with 5 V Supply  Small 1 µF Capacitors  Low Power Shutdown ≤ µA  Receivers Active in Shutdown (ADM223)  ±30 V Receiver Input Levels  Latch-Up FREE  Plug-In Upgrade for MAX223/230-241  Plug-In Upgrade for AD230–AD241 

5.7 kV rms, 849 VPEAK Working Voltage, Signal Isolated CAN-FD Transceiver Features: 5.7 kV rms (8000 VPEAK) signal isolated CAN transceiver 1.7 V to 5.5 V supply range for VDD1 4.5 V to 5.5 V supply range for VDD2 ISO 11898-2: 2016 compliant (CAN flexible data rate, CAN-FD) Data rates up to 12 Mbps for CAN-FD Low loop propagation delay of 145 ns max Extended common-mode range of ±25 V Bus fault protection (CANH, CANL) of ±40 V Low power standby supporting remote wake request Extra isolated signal for control (for example, termination switches) Slope control for reduced EMI Safety and regulatory approvals (pending) VDE Certificate of Conformity, VDE 0884-11 VIORM = 849 VPEAK VIOSM = 8000 VPEAK (Test: VPEAK = 12.8 kV) UL: 5700 V rms for 1 minute per UL1577 CSA Component Acceptance 5A at 5 kV rms IEC 60950, IEC 61010 8.3 mm creepage/clearance with 16-lead SOIC package High common-mode transient immunity: ≥75 kV/µs Industrial temperature range: −40°C to +125°C