The AD8339 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332 / AD8334 / AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4? local oscillator (LO) input that divides this signal and generates the necessary 0? and 90? phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input.Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5? phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45?, then the user can phase align Channel 2 with Channel 1 by choosing the correct code.The mixer outputs are in current form for convenient summation. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the AD8021?or the AD829. Following the current summation, the combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665?(16-bit, 570 kSPS).An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again.The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm ? 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.APPLICATIONS Medical imaging (CW ultrasound beamforming) Phased array systems Radar Adaptive antennas Communication receivers

The AD8341 vector modulator performs arbitrary amplitudeand phase modulation of an RF signal. Because the RF signalpath is linear, the original modulation is preserved. This part canbe used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be controlledfrom a maximum of ?4.5 dB to less than ?34.5 dB, and the phasecan be shifted continuously over the entire 360? range. For maximumgain, the AD8341 delivers an OP1dB of 8.5 dBm, an OIP3of 17.5 dBm, and an output noise floor of ?150.5 dBm/Hz,independent of phase. It operates over a frequency range of1.5 GHz to 2.4 GHz.The baseband inputs in Cartesian I and Q format control theamplitude and phase modulation imposed on the RF inputsignal. Both I and Q inputs are dc-coupled with a ?500 mVdifferential full-scale range. The maximum modulationbandwidth is 230 MHz, which can be reduced by adding externalcapacitors to limit the noise bandwidth on the control lines.Both the RF inputs and outputs can be used differentially orsingle-ended and must be ac-coupled. The RF input and outputimpedances are nominally 50 ? over the operating frequencyrange. The DSOP pin allows the output stage to be disabledquickly in order to protect subsequent stages from overdrive.The AD8341 operates off supply voltages from 4.75 V to 5.25 Vwhile consuming approximately 125 mA.The AD8341 is fabricated on Analog Devices? proprietary, highperformance 25 GHz SOI complementary bipolar IC process. Itis available in a 24-lead, lead-free LFCSP package and operatesover a ?40?C to +85?C temperature range. Evaluation boardsare available. Applications RF PA linearization/RF predistortion Amplitude and phase modulation Variable attenuators and phase shifters CDMA2000, WCDMA, GSM/EDGE linear power amplifiers Smart antennasAvailabilitySamples part number AD8341ACP and an evaluation board, part number AD8341-EVAL, are available.Companion ProductsAD8302 - LF - 2.7GHz RF/IF Gain Phase DetectorAD8340 - RF Vector Modulator 700MHz to 1000MHzOther Modulator / Demodulator ProductsAD8345 - 250MHz to 1000MHz Low Noise RF/IF ModulatorAD8346 - 800MHz to 2.5GHz Lower Power Direct Up-Conversion ModulatorAD8347 - 800MHz to 2.7GHz Direct Conversion DemodulatorAD8348 - 50MHz to 1000MHz RF/IF Quadrature DemodulatorAD8349 - 700MHz - 2.7GHz Low Noise Direct Up Conversion Modulator

The AD8361 is a mean-responding power detector for use inhigh frequency receiver and transmitter signal chains, up to2.5 GHz. It is very easy to apply. It requires a single supply onlybetween 2.7 V and 5.5 V, a power supply decoupling capacitor,and an input coupling capacitor in most applications. Theoutput is a linear-responding dc voltage with a conversion gainof 7.5 V/V rms. An external filter capacitor can be added toincrease the averaging time constant.The AD8361 is intended for true power measurement of simpleand complex waveforms. The device is particularly useful formeasuring high crest-factor (high peak-to-rms ratio) signals,such as CDMA and W-CDMA.The AD8361 has three operating modes to accommodate avariety of analog-to-digital converter requirements: Ground reference mode, in which the origin is zero. Internal reference mode, which offsets the output 350 mV above ground. Supply reference mode, which offsets the output to VS/7.5.The AD8361 is specified for operation from ?40?C to +85?Cand is available in 8-lead MSOP and 6-lead SOT-23 packages. Itis fabricated on a proprietary high fT silicon bipolar process.

The AD8364 is a true rms, responding, dual-channel RF powermeasurement subsystem for the precise measurement and controlof signal power. The flexibility of the AD8364 allows communicationssystems, such as RF power amplifiers and radio transceiverAGC circuits, to be monitored and controlled with ease. Operatingon a single 5 V supply, each channel is fully specified for operationup to 2.7 GHz over a dynamic range of 60 dB. The AD8364provides accurately scaled, independent, rms outputs of both RFmeasurement channels. Difference output ports, which measurethe difference between the two channels, are also available. Theon-chip channel matching makes the rms channel differenceoutputs extremely stable with temperature and process variations.The device also includes a useful temperature sensor with anaccurately scaled voltage proportional to temperature, specifiedover the device operating temperature range. The AD8364 canbe used with input signals having rms values from ?55 dBm to+5 dBm referred to 50 ? and large crest factors with noaccuracy degradation. Integrated in the AD8364 are two matched AD8362 channels(see the AD8362 data sheet for more information) with improvedtemperature performance and reduced log conformance ripple.Enhancements include improved temperature performance andreduced log-conformance ripple compared to the AD8362. On-chipwide bandwidth output operational amplifiers are connectedto accom-modate flexible configurations that support manysystem solutions.The device can easily be configured to provide four rmsmeasurements simultaneously. Linear-in-dB rms measurementsare supplied at OUTA and OUTB, with conveniently scaledslopes of 50 mV/dB. The rms difference between OUTA andOUTB is available as differential or single-ended signals atOUTP and OUTN. An optional voltage applied to VLVLprovides a common mode reference level to offset OUTP andOUTN above ground.The AD8364 is supplied in a 32-lead, 5 mm ? 5 mm LFCSP, forthe operating temperature of ?40?C to +85?C.Applications Wireless infrastructure power amplifier linearization/control Antenna VSWR monitor Gain and power control and measurement Transmitter signal strength indication (TSSI) Dual-channel wireless infrastructure radios

The AD8368 is a variable gain amplifier (VGA) with analog linear-in-dB gain control that can be used from low frequencies to 800 MHz. Its excellent gain range, conformance, and flatness are attributed to the Analog Devices, Inc. X-AMP? architecture, an innovative technique for implementing high performance variable gain control.The gain range of ?12 dB to +22 dB is scaled accurately to 37.5 dB/V with excellent conformance error. The AD8368 has a 3 dB bandwidth of 800 MHz that is nominally independent of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum gain. The output noise floor is ?143 dBm/Hz, which corresponds to a 9.5 dB noise figure at maximum gain. The single-ended input and output impedances are nominally 50 ?.The gain of the AD8368 can be configured to be an increasing or decreasing function of the gain control voltage depending on whether the MODE pin is pulled to the positive supply or to ground, respectively. When MODE is pulled high, the AD8368 operates as a typical VGA with increasing gain.By connecting MODE to ground and using the on-board rms detector, the AD8368 can be configured as a complete automatic gain control (AGC) system with RSSI. The output power is accurately leveled to the internal default setpoint of 63 mV rms (?11 dBm referenced to 50 ?), independent of the waveform crest factor. Because the uncommitted detector input is available at DETI, the AGC loop can level the signal at the AD8368 output or at any other point in the signal chain over a maximum input power range of 34 dB. Furthermore, the setpoint level can be raised by dividing down the output signal before applying it to the detector.The AD8368 operates from a supply voltage of 4.5 V to 5.5 V and consumes 60 mA of current. It can be fully powered down to <3 mA by grounding the ENBL pin. The AD8368 is fabricated using the Analog Devices proprietary SiGe SOI complementary bipolar IC process. It is available in a 24-lead LFCSP and operates over the industrial temperature range of ?40?C to +85?C. Application boards are available upon request.ApplicationsComplete IF AGC amplifiers Gain trimming and leveling Cellular base stations Point-to-point radio links RF instrumentation Data Sheet, Rev. B, 09/2008

The AD9081 mixed signal front end (MxFE?) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. Two models for the AD9081 are offered. The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.APPLICATIONS Wireless communications infrastructure Microwave point-to-point, E-band and 5G mmWave Broadband communications systems DOCSIS 3.1 and 4.0 CMTS Phased array radar and electronic warfare Electronic test and measurement systems

The AD9094 is an 8-bit, 1 GSPS, quad analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed to sample wide bandwidth analog signals up to 1.4 GHz. The AD9094 is optimized for wide input bandwidth, a high sampling rate, high works linearity, and low power in a small package. The quad-ADC cores feature multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs that support a variety of user-selectable input ranges. An integrated voltage reference facilitates design considerations. The analog inputs and clock signals are differential inputs. Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of JESD204B Subclass 1 or Subclass 0, high speed, serialized outputs, depending on the sample rate and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, SYNCINB?AB, and SYNCINB?CD input pins. The AD9094 has flexible power-down options that allow significant power savings when desired. To program the power down options, use the 1.8 V capable, serial port interface (SPI). The AD9094 is available in a Pb-free, 72-lead, lead frame chip scale package (LFCSP) and is specified over a junction temperature range of ?40?C to +105?C. This product may be protected by one or more U.S. or international patents. Note that throughout the data sheet, multifunction pins, such as PDWN/STBY, are referred to either by the entire pin name or by a single function of the pin, for example, PDWN, when only that function is relevant. PRODUCT HIGHLIGHTS Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide, full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.APPLICATIONSLaser imaging, detection, and ranging (LIDAR)CommunicationsDigital oscilloscope (DSO)Ultrawideband satellite receiversInstrumentation

The AD9106 TxDAC? and waveform generator is a high performance, quad digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform generation with a direct digital synthesizer (DDS). The DDS is a 12-bit output, up to 180 MHz master clock sinewave generator with a 24-bit tuning word allowing 10.8 Hz/LSB frequency resolution. The DDS has a single frequency output for all four DACs and independent programmable phase shift outputs for each of the four DACs.SRAM data can include directly generated stored waveforms, amplitude modulation patterns applied to DDS outputs, or DDS frequency tuning words.An internal pattern control state machine allows the user to program the pattern period for all four DACs as well as the start delay within the pattern period for the signal output on each DAC channel.Registers accessed using the serial peripheral interface (SPI) configure the digital waveform generator and load patterns into the SRAM.There are gain adjustment factors and offset adjustments applied to the digital signals on their way into the four DACs.The AD9106 offers exceptional ac and dc performance and supports DAC sampling rates up to 180 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9106 make it well suited for portable and low power applications.Applications Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9119/AD9129 are high performance, 11-/14-bit RF digital-to-analog converters (DACs) supporting data rates up to 2.85 GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode? or 2? interpolation. The high dynamic range and bandwidth enable multicarrier generation up to 4.2 GHz.In baseband mode, wide bandwidth capability combines with high dynamic range to support from 1 to 158 contiguous carriers for CATV infrastructure applications. A choice of two optional 2? interpolation filters is available to simplify the postreconstruction filter by effectively increasing the DAC update rate by a factor of 2. In Mix-Mode operation, the AD9119/AD9129 can reconstruct RF carriers in the second and third Nyquist zone while still maintaining exceptional dynamic range up to 4.2 GHz. The high performance NMOS DAC core features a quad-switch architecture that enables industry-leading direct RF synthesis performance with minimal loss in output power. The output current can be programmed over a range of 9.5 mA to 34.4 mA.The AD9119/AD9129 include several features that may further simplify system integration. A dual-port, source synchronous LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the integrity of the interface. On-chip delay locked loops (DLLs) optimize timing between different clock domains.A serial peripheral interface (SPI) configures the AD9119/ AD9129 and monitors the status of readback registers. The AD9119/AD9129 are manufactured on a 0.18 ?m CMOS process and operates from +1.8 V and ?1.5 V supplies. It is supplied in a 160-ball chip scale package ball grid array.Product Highlights High dynamic range and signal reconstruction bandwidth support RF signal synthesis of up to 4.2 GHz. Dual-port interface with double data rate (DDR) LVDS data receivers supports 2850 MSPS maximum conversion rate. Manufactured on a CMOS process; a proprietary switching technique enhances dynamic performance.Applications Broadband communications systems CMTS/VOD Wireless infrastructure: W-CDMA, LTE, point-to-point Instrumentation, automatic test equipment (ATE) Radar, jammers

The AD9161 is a high performance, 11-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2? interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.In baseband mode, wide bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of two carriers to full maximum spectrum of 1.794 GHz. A 2? interpolator filter (FIR85) enables the AD9161/AD9162 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode? operation, the AD9161/AD9162 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9161/AD9162 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.A serial peripheral interface (SPI) can configure the AD9161/AD9162 and monitor the status of all registers. The AD9161/AD9162 are offered in an 165-ball, 8.0 mm ? 8.0 mm, 0.5 mm pitch, CSP_BGA package and in an 169-ball, 11 mm ? 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option for the AD9162.Product Highlights High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance with margin.Applications Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure W-CDMA, LTE, LTE-A, point to point Instrumentation, automatic test equipment (ATE) Radars and jammers