The AD8307 is the first logarithmic amplifier made available in an 8-lead SOIC_N package. It is a complete 500 MHz monolithic demodulating logarithmic amplifier based on the progressive compression (successive detection) technique, providing a dynamic range of 92 dB to ±3 dB law conformance and 88 dB to a tight ±1 dB error bound at all frequencies up to 100 MHz. The AD8307 is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 7.5 mA is needed. A fast acting CMOS-compatible control pin can disable the AD8307 to a standby current of 150 μA.The AD8307 operates over the industrial temperature range of −40°C to +85°C and is available in an 8-lead SOIC package and an 8-lead PDIP.Applications Conversion of signal level to decibel form  Transmitter antenna power measurement  Receiver signal strength indication (RSSI)  Low cost radar and sonar signal processing  Network and spectrum analyzers (to 120 dB)  Signal level determination down to 20 Hz  True decibel ac mode for multimeters

The AD8400 / AD8402 / AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kOhm, 10 kOhm, 50 kOhm or 100 kOhm has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.APPLICATIONS Mechanical potentiometer replacement Programmable filters, delays, time constants Volume control, panning Line impedance matching Power supply adjustment

The AD8400/AD8402/AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kOhm, 10 kOhm, 50 kOhm or 100 kOhm has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.

The HMC311SC70(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) Gain Block MMIC SMT DC to 8 GHz amplifier. Packaged in an industry standard SC70, the amplifier can be used as either a cascadable 50 Ohm gain stage or to drive the LO port of HMC mixers with up to +15 dBm output power. The HMC311SC70(E) offers 15 dB of gain and an output IP3 of +30 dBm while requiring only 54 mA from a +5V supply. The Darlington topology results in reduced sensitivity to normal process variations, and yields excellent gain stability over temperature while requiring a minimal number of external bias components.Applications Cellular / PCS / 3G WiBro / WiMAX / 4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment

The HMC1034LP6GE is a low-noise, wide-band clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 125MHz and 3GHz range. The HMC1034LP6GE features low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC1034LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-165dBc/Hz) makes the HMC1034LP6GE an ideal source for a variety of applications–such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SERDES) circuits, FPGAs and processors. The HMC1034LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1034LP6GE includes a 2-bit output amplitude control which may be set via the SPI serial programming interface, and an output Mute function. The Delta-Sigma Modulator of the HMC1034LP6GE features Hittite’s Exact Frequency Mode, which enables users to generate output frequencies with close to 0 Hz frequency error.APPLICATIONS 10G/40G/100G Optical Modules, Transponders, Line Cards OTN and SONET/SDH Applications 1G/10G Ethernet Line Cards High Frequency Processor Clocks Low Jitter SAW Oscillator Replacement  Fiber Channel Interface Clocks Cellular/4G Infrastructure DDS Replacement 10G Optical Modules, Transponders, Line Cards

The HMC1035LP6GE is a low-noise, wide-band 3.3 V clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 25 MHz and 2500 MHz range. The HMC1035LP6GE features a low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance.The HMC1035LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-162 dBc/Hz) makes the HMC1035LP6GE an ideal source for a variety of applications–such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SER DES) circuits, FPGAs and processors. The HMC1035LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1035LP6GE can be set to either External Termination, which could be used for LVPECL operation, or Internal Termination for operation in an LVDS compatible mode or LVPECL. Additionally, an ouput swing adjustment makes the device flexible and compatible with a wide variety of signal level requirements. The output can be internally terminated to reduce component count and cost or could be terminated externally using standard LVPECL termination methods. An Output Mute function allows the user to shut off the outputs, such as may be required for board testing or debugging. The LVPECL/LVDS, amplitude select and Output Mute function are all programmed SPI serial programming.The HMC1035LP6GE is designed to select between a Power Priority or a Performance Priority mode. The Power Priority setting reduces the current consumption of the part, whereas the Performance Priority setting improves the Jitter and Phase Noise performance.The 24 bit Delta-Sigma Modulator further enhances Hittite’s Exact Frequency Mode, which enables users to generate output frequencies with 0 Hz frequency error in many applications.APPLICATIONS 10G/40G/100G Optical Modules, Transponders, Line Cards OTN and SONET /SDH Applications Data Converters, Sample Clock Generation Cellular/4G Infrastructure High Frequency Processor/FPGA Clocks Any Frequency Clock Rate Generation Low Jitter SAW Oscillator Replacement DDS Replacement Frequency Translation Frequency Margining

The HMC207AS8E is a miniature double- balanced mixer in an 8 lead plastic surface mount Small Outline IC (SOIC) package. This passive MMIC mixer is constructed of GaAs Schottky diodes and novel planar transformer baluns on the chip. The device can be used as an upconverter, downconverter, biphase modulator (de)modulator, or phase comparator. The consistent MMIC performance will improve system operation and assure regulatory compliance. The high LO suppression of 45 to 50 dB yields excellent carrier suppression for modulator applications.Applications Base Stations  Cable Modems  Portable Wireless

The HMC311SC70(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) Gain Block MMIC SMT DC to 8 GHz amplifier. Packaged in an industry standard SC70, the amplifier can be used as either a cascadable 50 Ohm gain stage or to drive the LO port of HMC mixers with up to +15 dBm output power. The HMC311SC70(E) offers 15 dB of gain and an output IP3 of +30 dBm while requiring only 54 mA from a +5V supply. The Darlington topology results in reduced sensitivity to normal process variations, and yields excellent gain stability over temperature while requiring a minimal number of external bias components.Applications Cellular / PCS / 3G WiBro / WiMAX / 4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment

The HMC609LC4 is a GaAs PHEMT MMIC Low Noise Amplifier (LNA) which operates from 2 to 4 GHz. The HMC609LC4 features extremely flat performance characteristics including 20 dB of small signal gain, 3.5 dB of noise figure and output IP3 of +36.5 dBm across the operating band. This 50 Ohm matched amplifier does not require any external matching components. The HMC609LC4 is compatible with high volume surface mount manufacturing techniques, and the RF I/Os are DC blocked for further ease of integration.Applications Fixed Microwave Test & Measurement Equipment Radar & Sensors Military & Space

The HMC611LP4(E) Logarithmic Detector/Controller converts RF signals at its input, to a proportional DC voltage at its output. The HMC611LP4(E) employs a successive compression topology which delivers extremely high dynamic range and conversion accuracy over a wide input frequency range. As the input power is increased, successive amplifiers move into saturation one by one creating an accurate approximation of the logarithm function.The output of a series of square law detectors is summed, converted into voltage domain and buffered to drive the LOGOUT output. For detection mode, the LOGOUT pin is shorted to the VSET input, and will provide a nominal logarithmic slope of -25mV/dB and an intercept of 18 dBm (22 dBm for ƒ ≥ 5.8 GHz). The HMC611LP4(E) can also be used in the controller mode where an external voltage is applied to the VSET pin, to create an AGC or APC feedback loop.Applications Cellular/PCS/3G WiMAX, WiBro, WLAN, Fixed Wireless & Radar Power Monitoring & Control Circuitry Receiver Signal Strength Indication (RSSI) Automatic Gain & Power Control