Precision Analog Microcontroller, 16-Bit Analog Input/Output with MDIO Interface, Arm Cortex-M33 Features: Analog input/output Multichannel, 16-bit, 2 MSPS ADC Up to 16 external channels On-chip die temperature monitor 4 power monitor channels 4 PGA/TIA channels supporting voltage and current measurements Fully differential and single-ended modes 0 V to VREF analog input range 12-bit voltage output DACs 8× 0 V to 2.5 V, 1 kΩ load 4× 0 V to 2.5 V, 2.5 kΩ load On-chip low drift voltage reference, 1.25 V or 2.5 V Buffered 1.25 V or 2.5 V output 4 voltage comparators Microcontroller 32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU Serial wire port supports code download and debug Clocking options 16 MHz on-chip oscillator 160 MHz PLL output with programmable divider External clock source Memory 2× 512 kB independent Flash/EE memories 10,000-cycle Flash/EE endurance 20-year Flash/EE retention 128 kB SRAM with ECC Software triggered, in circuit reprogrammability via MDIO or I2C On-chip peripherals 2× UART, 3× SPI, 3× I2C serial input/output Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs MDIO slave up to 10 MHz 5 general-purpose timers Wake-up timer (WUTs) Watchdog timers (WDTs) 32-element PLA 16-bit PWM 10 external Interrupts Power Multiple supplies: 3.3 V for voltage DACs and ADCs, and 3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs Flexible operating modes for low power applications Packages and temperature range 5 mm × 5 mm 81-ball CSP_BGA and 3.46 mm × 3.46 mm 64-ball WLCSP BGA package uses ULA molding compounds Fully specified for −40°C to +105°C operation Tools Low cost quick start development system Full third-party support  

3.0 kV rms, Dual-Channel Digital Isolators Features: High common-mode transient immunity: 100 kV/µs typical High robustness to radiated and conducted noise Low propagation delay 13 ns maximum for 5 V operation 15 ns maximum for 1.8 V operation 150 Mbps minimum data rate Safety and regulatory approvals UL recognition: 3000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate of conformity DIN VDE V 0884-11:2017-01 VIORM = 565 V peak CQC certification per GB4943.1-2011 Backward compatibility ADuM120N0 pin-compatible with ADuM1285 ADuM120N1 pin-compatible with ADuM1280 and ADuM1200 ADuM121N0 pin-compatible with ADuM1286 ADuM121N1 pin-compatible with ADuM1281 and ADuM1201 Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C Failsafe high or low options 8-lead, RoHS-compliant, SOIC package Qualified for automotive applications

Micropower, Dual-Channel Digital Isolators, Default High (2/0 Channel Directionality) Features: Ultralow power operation 3.3 V operation 6 μA per channel quiescent current, refresh enabled 0.3 μA per channel quiescent current, refresh disabled 148 μA/Mbps per channel typical dynamic current 2.5 V operation 3 μA per channel quiescent current, refresh enabled 0.1 μA per channel quiescent current, refresh disabled Quad-channel products available See datasheet for additional features

Quad-Channel Digital Isolator (3/1 Channel Directionality) Features: Qualified for automotive applications Low power operation Bidirectional communication 3 V/5 V level translation High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics High common-mode transient immunity: >25 kV/μs See data sheet for additional features

Triple-Channel, Digital Isolator, Enhanced System-Level ESD Reliability (2/1 channel directionality) Features: Enhanced system-level ESD performance per IEC 61000-4-x Low power operation 5 V operation 2.0 mA per channel maximum at 0 Mbps to 2 Mbps 4.1 mA per channel maximum at 10 Mbps 36 mA per channel maximum at 90 Mbps 3.3 V operation 1.0 mA per channel maximum at 0 Mbps to 2 Mbps 2.8 mA per channel maximum at 10 Mbps 17 mA per channel maximum at 90 Mbps Bidirectional communication 3.3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body, RoHS-compliant package Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak CQC Certification per GB4943.1-2011

Isolated Switching Regulators (3/1 Channel Directionality) Features: Isolated PWM Controller Integrated transformer driver Regulated adjustable output: 3.3 V to 24 V 2 W output power 70% efficiency at guaranteed load of 400 mA at 5.0 V output Quad dc-to-25 Mbps (NRZ) signal isolation channels 20-lead SSOP package High temperature operation: 105°C High common-mode transient immunity: >25 kV/μs 200 kHz to 1 MHz adjustable oscillator frequency Soft start function at power-up Pulse-by-pulse overcurrent protection Thermal shutdown 2500 V rms isolation Evaluation Board available Automotive Qualified

15V, 5A Synchronous Step-Down Regulator Features: High Efficiency: Up to 96% 5A Output Current 4V to 15V VIN Range Integrated Power N-Channel MOSFETs (70mΩ Top and 35mΩ Bottom) Adjustable Frequency 800kHz to 4MHz PolyPhase® Operation (Up to 12 Phases) Output Tracking 0.6V ±1% Reference Accuracy Current Mode Operation for Excellent Line and Load Transient Response Shutdown Mode Draws Less Than 15μA Supply Current Available in 24-Pin (4mm × 4mm) QFN Package AEC-Q100 Qualified for Automotive Applications

Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock See data sheet for additional features

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity