The ADP5024 combines two high performance buck regulators and one low dropout (LDO) regulators in a small, 24-lead 4 mm × 4 mm LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above a predefined threshold. When the load current falls below a pre-defined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. The two bucks operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the LDO extends the battery life of portable devices. The ADP5024 LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.Regulators in the ADP5024 are activated though dedicated enable pins. The default output voltages can be either externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version.APPLICATIONS Power for processors, ASICS, FPGAs, and RF chipsets Portable instrumentation and medical devices Space constrained devices

The ADP5061 charger is fully compliant with USB 3.0 and the USB Battery Charging Specification 1.2 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.The ADP5061 operates from a 4 V to 6.7 V input voltage range but is tolerant of voltages up to 20 V. The 20 V voltage tolerance alleviates the concerns about the USB bus spiking during disconnect or connect scenarios.The ADP5061 features an internal FET between the linear charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no batteryscenario, which allows for immediate system function on connection to a USB power supply.Based on the type of USB source, which is detected by an external USB detection chip, the ADP5061 can be set to apply the correct current limit for optimal charging and USB compliance.The ADP5061 has three factory programmable digital input/output pins that provide maximum flexibility for different systems. These digital input/output pins permit combinations of features such as, input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin. APPLICATIONS Digital still cameras Digital video cameras Single cell Li-Ion portable equipment PDAs, audio, GPS devices Portable medical devices Mobile phones

The ADP5134 combines two high performance buck regulators and two low dropout (LDO) regulators. It is available in a 24-lead 4 mm × 4 mm LFCSP.The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set to high, the buck regulators operate in forced pulse-width modulation (PWM) mode. When the MODE pin is set to low, the buck regulators operate in PWM mode when the load is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency.The two buck regulators operate out of phase to reduce the input capacitor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5134 LDO regulators extend the battery life of portable devices. The ADP5134 LDO regulators maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage of 500 mV.Regulators in the ADP5134 are activated through dedicated enable pins. The default output voltages can be externally set in the adjustable version or factory programmable to a wide range of preset values in the fixed voltage version.Applications Power for processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and radio frequency (RF) chipsets Portable instrumentation and medical devices Space constrained devices

The ADP5585 is a 10I/O port expander with built-in keypad matrix decoder, programmable logic, reset generator, and PWM generator. I/O expander ICs are used in portable devices (phones, remote controls, & cameras) and non-portable applications (healthcare, industrial & instrumentation). I/O expanders can be used to increase the number of I/Os available to a processor or to reduce the number of I/Os required through interface connectors for front panel designs.The ADP5585 handles all key scanning and decoding and can flag the main processor via an interrupt line that new key events have occurred. GPI changes and logic changes can also be tracked as events via the FIFO, eliminating the need to monitor different registers for event changes. The ADP5585 is equipped with a FIFO to store up to 16 events. Events can be read back by the processor via an I2C compatible interface.The ADP5585 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other functions.The programmable logic functions allow common logic requirements to be integrated as part of the GPIO expander, saving board area and cost.APPLICATIONS Keypad entries and input/output expansion capabilities Smart phones, remote controls, and cameras Healthcare, industrial, and instrumentation

The ADP7102 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 μF ceramic output capacitor. The ADP7102 is available in seven fixed output voltage options and an adjustable version, which allows output voltages that range from 1.22 V to VIN − VDO via an external feedback divider. The ADP7102 output noise voltage is 15 μV rms and is independent of the output voltage. A digital power good output allows power system monitors to check the health of the output voltage. A user programmable precision undervoltage lockout function facilitates sequencing of multiple power supplies. The ADP7102 is available in 8-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages. The LFCSP offers a very compact solution and also provides excellent thermal performance for applications requiring up to 300 mA of output current in a small, low-profile footprint. APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation

The ADP7102 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 μF ceramic output capacitor. The ADP7102 is available in seven fixed output voltage options and an adjustable version, which allows output voltages that range from 1.22 V to VIN − VDO via an external feedback divider. The ADP7102 output noise voltage is 15 μV rms and is independent of the output voltage. A digital power good output allows power system monitors to check the health of the output voltage. A user programmable precision undervoltage lockout function facilitates sequencing of multiple power supplies. The ADP7102 is available in 8-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages. The LFCSP offers a very compact solution and also provides excellent thermal performance for applications requiring up to 300 mA of output current in a small, low-profile footprint. APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation

The AD5761R/AD5721R are single channel, 16-/12-bit serialinput, voltage output, digital-to-analog converters (DACs).They operate from single supply voltages from +4.75 V to+30 V or dual supply voltages from −16.5 V to 0 V VSS and+4.75 V to +16.5 V VDD. The integrated output amplifier,reference buffer, and reference provide a very easy to use,universal solution.The devices offer guaranteed monotonicity, integral nonlinearity(INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settlingtime on selected ranges.The AD5761R/AD5721R use a serial interface that operates atclock rates of up to 50 MHz and are compatible with DSP andmicrocontroller interface standards. Double buffering allows theasynchronous updating of the DAC output. The input codingis user-selectable twos complement or straight binary. Theasynchronous reset function resets all registers to their defaultstate. The output range is user selectable, via the RA[2:0] bitsin the control register.The devices available in a 3 mm × 3 mm LFCSP package and a16-lead TSSOP package offer guaranteed specifications over the−40°C to +125°C industrial temperature range.Applications Industrial automation Instrumentation, data acquisition Open-/closed-loop servo control, process control Programmable logic controllers

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

The AD7124-8 is a low power, low noise, completely integratedanalog front end for high precision measurement applications.The device contains a low noise, 24-bit Σ-Δ analog-to-digitalconverter (ADC), and can be configured to have 8 differentialinputs or 15 single-ended or pseudo differential inputs. The onchiplow gain stage ensures that signals of small amplitude canbe interfaced directly to the ADC.One of the major advantages of the AD7124-8 is that it gives theuser the flexibility to employ one of three integrated powermodes. The current consumption, range of output data rates,and rms noise can be tailored with the power mode selected.The device also offers a multitude of filter options, ensuring thatthe user has the highest degree of flexibility.The AD7124-8 can achieve simultaneous 50 Hz and 60 Hzrejection when operating at an output data rate of 25 SPS (singlecycle settling), with rejection in excess of 80 dB achieved at loweroutput data rates.The AD7124-8 establishes the highest degree of signal chainintegration. The device contains a precision, low noise, lowdrift internal band gap reference and accepts an externaldifferential reference, which can be internally buffered. Otherkey integrated features include programmable low drift excitationcurrent sources, burnout currents, and a bias voltage generator,which sets the common-mode voltage of a channel to AVDD/2.The low-side power switch enables the user to power downbridge sensors between conversions, ensuring the absoluteminimal power consumption of the system. The device alsoallows the user the option of operating with either an internalclock or an external clock.The integrated channel sequencer allows several channels to beenabled simultaneously, and the AD7124-8 sequentially convertson each enabled channel, simplifying communication with thedevice. As many as 16 channels can be enabled at any time, achannel being defined as an analog input or a diagnostic suchas a power supply check or a reference check. This uniquefeature allows diagnostics to be interleaved with conversions.The AD7124-8 also supports per channel configuration. Thedevice allows eight configurations or setups. Each configurationconsists of gain, filter type, output data rate, buffering, andreference source. The user can assign any of these setups on achannel by channel basis.The AD7124-8 also has extensive diagnostic functionalityintegrated as part of its comprehensive feature set. Thesediagnostics include a cyclic redundancy check (CRC), signalchain checks, and serial interface checks, which lead to a morerobust solution. These diagnostics reduce the need for externalcomponents to implement diagnostics, resulting in reducedboard space needs, reduced design cycle times, and cost savings.The failure modes effects and diagnostic analysis (FMEDA) of atypical application has shown a safe failure fraction (SFF) greaterthan 90% according to IEC 61508.The device operates with a single analog power supply from 2.7 Vto 3.6 V or a dual 1.8 V power supply. The digital supply has arange of 1.65 V to 3.6 V. It is specified for a temperature rangeof −40°C to +125°C. The AD7124-8 is housed in a 32-leadLFCSP package.Note that, throughout this data sheet, multifunction pins, suchas DOUT/RDY, are referred to either by the entire pin name orby a single function of the pin, for example, RDY, when onlythat function is relevant.Applications Temperature measurement Pressure measurement Industrial process control Instrumentation Smart transmitters

The AD7177-2 is a 32-bit low noise, fast settling, multiplexed,2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digitalconverter (ADC) for low bandwidth inputs. It has a maximumchannel scan rate of 10 kSPS (100 µs) for fully settled data. Theoutput data rates range from 5 SPS to 10 kSPS.The AD7177-2 integrates key analog and digital signal conditioningblocks to allow users to configure an individual setup foreach analog input channel in use. Each feature can be user selectedon a per channel basis. Integrated true rail-to-rail buffers on theanalog inputs and external reference inputs provide easy to drivehigh impedance inputs. The precision 2.5 V low drift (2 ppm/°C)band gap internal reference (with output reference buffer) addsembedded functionality to reduce external component count.The digital filter allows simultaneous 50 Hz and 60 Hz rejectionat a 27.27 SPS output data rate. The user can switch betweendifferent filter options according to the demands of eachchannel in the application. The ADC automatically switchesthrough each selected channel. Further digital processingfunctions include offset and gain calibration registers,configurable on a per channel basis.The device operates with a 5 V AVDD1 supply, or with ±2.5 VAVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies.The specified operating temperature range is −40°C to +105°C.The AD7177-2 is available in a 24-lead TSSOP package.Applications Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography