Dual-core SHARC+ and Arm Cortex-A5 SOC, DDR, Ethernet, USB, 349-cspBGA Features:SHARC+ Core Infrastructure: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 450 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory: 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers: DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators: FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging: 19mm x 19mm BGA (0.8mm pitch) Commercial, Industrial & AutomotivePeripherals: Gigabit Ethernet MAC (RGMII) With IEEE-1588 & AVB support (QoS & clock recovery) USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 MLB 3/6-pin (Auto devices only) Up to 8x Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG 2x Dual-SPI and 1x QuadSPI (w/ direct execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM, ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 80 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor

Dual-core SHARC+ and ARM Cortex-A5 SOC, dual DDR, 2xEthernet, 2xUSB, SDIO, PCIe, 529-cspBGA Features: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 500 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging 19mm x 19mm BGA  (0.8mm pitch) Commercial, Industrial & Automotive 2x Ethernet MAC One Gigabit (RGMII) and one 10/100 (RMII) With IEEE-1588 & AVB support (QoS & clock recovery) 2x USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 SD/SDIO/MMC/eMMC (with SDXC support) PCIe2.0 (1 lane) (SC589 only) Up to 8 Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG  2x Dual-SPI and 1x QuadSPI (w/ direct  execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM,  ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 102 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor

Low Cost JFET Input Operational Amplifier Features: TL082/TL084 compatible Low input bias current: 10 pA maximum Offset voltage 5.5 mV maximum (ADTL082A/ADTL084A) 9 mV maximum (ADTL082J/ADTL084J) ±15 V operation Low noise: 16 nV/√Hz Wide bandwidth: 5 MHz Slew rate: 20 V/μs CMRR: 80 dB minimum Total harmonic distortion: 0.001% Supply current: 1.2 mA typical Unity-gain stable

Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU Features: Analog I/O Multichannel, 12-bit, 1 MSPS ADC Up to 16 ADC channels Fully differential and single-ended modes 0 V to VREF analog input range12-bit voltage output DACs Up to 4 DAC outputs available On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 44 MHz 41.78 MHz PLL with programmable divider See datasheet for additional features

MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU Features: High resolution Σ-Δ ADCs 2 independent 24-bit ADCs Up to 10 ADC input channels on all devices 24-bit no missing codes 22-bit rms (19.5 bit p-p) effective resolution Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled Memory 62-kbyte on-chip Flash/EE program memory 4-kbyte on-chip Flash/EE data memory Flash/EE, 100-year retention, 100 kcycle endurance 3 levels of Flash/EE program memory security In-circuit serial download (no external hardware) High speed user download (5 sec) 2304 bytes on-chip data RAM See data sheet for additional features

Microprocessor Supervisory Circuit in 3-Lead SC70, Active-Low Open-Drain Output Features: Specified over temperature Low power consumption (17 μA) Precision voltage monitor: 2.5 V, 3 V, 3.3 V, 5 V options Reset assertion down to 1 V VCC 140 ms minimum power-on reset Open-drain RESET output

Supervisory Circuit with Manual Reset, Active-Low Open-Drain and Active-High Push-Pull Reset Outputs Features: 27 reset threshold options 2.5 V to 5 V in 100 mV increments 4 reset timeout options 1 ms, 20 ms, 140 ms, and 1120 ms (minimum) 4 watchdog timeout options 6.3 ms, 102 ms, 1.6 sec, and 25.6 sec (typical) Manual reset input Multiple reset output options Low power consumption Specified over wide temperature range (−40°C to +125°C) Qualified for automotive applications 5-lead SOT-23 package

Ultralow Power Voltage Detector with Disable Input and Low Threshold Voltages Features: Ultralow power consumption with ICC = 92 nA (typical) Precision, low voltage monitoring Pretrimmed voltage monitoring threshold options 20 options from 0.5 V to 1.9 V ±1.3% threshold accuracy over full temperature range Output disable input 23 µs to 26 µs typical propagation delay Open-drain type output Power supply glitch immunity Available in a 1.46 mm × 0.96 mm WLCSP Operational temperature range: −40°C to +85°C

K Band Quadrature Demodulator with Integrated Fractional-N PLL and VCO Features: Fractional-N synthesizer with low phase noise VCO K band quadrature demodulator Programmable via 4-wire SPI RF operating frequency range: 17 GHz to 22 GHz LO internal frequency range: 17 GHz to 21.5 GHz Double sideband noise figure: 5 dB at maximum conversion gain Output integrated phase noise, 1 kHz to 10 MHz: <1° Maximum conversion gain of >50 dB Conversion gain control range of >50 dB IM3 of −54 dBc at −30 dBm composite input level, ΔfRF = 1 MHz 3 baseband, SPI-selectable LPFs with corner frequencies of: 125 MHz, 250 MHz, and 500 MHz on each baseband path

2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter Features: Digitally tunable, multioctave, high-pass and low-pass tuning Independent 3 dB frequency control for up to 4 GHz of bandwidth Optimal wideband rejection: 35 dB Single chip replacement for discrete filter banks Compact 9 mm × 9 mm, 56-terminal LGA packageENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard Military temperature range of −55°C to +105°C Controlled manufacturing baseline One assembly and test site One fabrication site Production change notification Qualification data available on request V62/21604