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TLV376IDR

Texas Instruments TLV376IDR

TLV5616CDR

Texas Instruments TLV5616CDR

TLV5616IDGKR

Texas Instruments TLV5616IDGKR

TLV5619IPWR

Texas Instruments TLV5619IPWR

TLV5623CDR

Texas Instruments TLV5623CDR

TLV5633CPW

Texas Instruments TLV5633CPW

TLV5638ID

Texas Instruments TLV5638ID

TLV5638IDR

Texas Instruments TLV5638IDR

TLV6001RIDBVT

Texas Instruments TLV6001RIDBVT

TLV62080DSGT

Texas Instruments TLV62080DSGT

Price $1.19
RoHS Compliant Yes Compliant Compliant Compliant Yes Yes Compliant Yes Compliant
Lead Status No Yes No No No Yes Yes No Yes No
Iq per channel(Typ)(mA) 0.815 0.075
Rating Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog
GBW(Typ)(MHz) 5.5 1
Operating Temperature Range(C) -40 to 125 -40 to 85,0 to 70 -40 to 85,0 to 70 0 to 70,-40 to 85 -40 to 85,0 to 70 -40 to 85,0 to 70 -40 to 125,-40 to 85,0 to 70 -40 to 125,-40 to 85,0 to 70 -40 to 125 -40 to 125
CMRR(Typ)(dB) 88 76
Offset Drift(Typ)(uV/C) 1 2
Package Group SOIC,SOT-23 PDIP,SOIC,VSSOP PDIP,SOIC,VSSOP SOIC,TSSOP SOIC,VSSOP TSSOP,SOIC SOIC SOIC SC70,SOT-23 WSON
CMRR(Min)(dB) 72 60
Approx. Price (US$) 0.46 | 1ku 3.42 | 1ku 3.42 | 1ku 5.04 | 1ku 1.10 | 1ku 5.58 | 1ku 5.52 | 1ku 5.52 | 1ku 0.17 | 1ku 0.45 | 1ku
Vos (Offset Voltage @ 25C)(Max)(mV) 0.100 4.5
Output Current(Typ)(mA) 30 15
Vn at 1kHz(Typ)(nV/rtHz) 8 28
Architecture CMOS CMOS
Rail-to-Rail In,Out In,Out
Iq per channel(Max)(mA) 1.2 0.1
Package Size mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2
Total Supply Voltage(Max)(+5V=5, +/-5V=10) 5.5 5.5
Slew Rate(Typ)(V/us) 2 0.5
Number of Channels(#) 1 1
Total Supply Voltage(Min)(+5V=5, +/-5V=10) 2.2 1.8
Additional Features Cost Optimized Cost Optimized,EMI Hardened
Output Type Buffered Voltage Buffered Voltage Buffered Voltage Buffered Voltage Buffered Voltage Buffered Voltage Buffered Voltage
Offset Error(Max)(%) N/A N/A N/A N/A N/A N/A N/A
Code to Code Glitch(Typ)(nV-sec) 10 10 5 10 5 5 5
Interface SPI SPI Parallel SPI Parallel SPI SPI
Settling Time(s) 3 3 1 3 1 1 1
Priority 1 1 1 1 1 1 1
Resolution(Bits) 12 12 12 8 12 12 12
Internal Reference Drift(Max)(ppm/degC) N/A N/A N/A N/A N/A N/A N/A
Output Range Min.(mA/V) 0 0 0 0 0 0 0
Special Features N/A N/A N/A N/A N/A N/A N/A Enable,Light Load Efficiency,Output Discharge,Power Good,Pre-Bias Start-Up,Synchronous Rectification,UVLO Fixed
DAC Architecture String String String String String String String
Output Range Max.(mA/V) 5.1 5.1 5.1 5.1 5.1 5.1 5.1
Zero Code Error(Typ)(mV) 10 10 20 10 20 24 24
Gain Error(Max)(%FSR) 0.6 0.6 0.5 0.6 0.3 0.6 0.6
INL(Max)(+/-LSB) 4 4 4 0.5 3 4 4
Power Consumption(Typ)(mW) 0.9 0.9 4.3 2.1 2.7 4.5 4.5
Reference Type Type Type Type Type Type Type
Sample / Update Rate(MSPS) 0.102 0.102 1 0.102 0.286 0.233 0.233
DAC Channels Channels Channels Channels Channels Channels Channels
Input Bias Current(Max)(pA) 76
Iq(Typ)(mA) 0.03
Switching Frequency(Min)(kHz) 2000
Vout(Max)(V) 4
Duty Cycle(Max)(%) 100
Vout(Min)(V) 0.5
Vin(Max)(V) 6
Type Converter
Regulated Outputs(#) 1
Switching Frequency(Max)(kHz) 2000
Iout(Max)(A) 1
Vin(Min)(V) 2.5
Control Mode Constant on-time (COT)