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TLV271CDBVT

Texas Instruments TLV271CDBVT

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TLV5616CDR

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TLV5616IDGKR

Texas Instruments TLV5616IDGKR

Price $3.26
RoHS Yes Compliant Yes Compliant Compliant Compliant Compliant Compliant Yes Compliant
Lead Status Yes No Yes No No No No No Yes No
GBW(Typ)(MHz) 3 3 5.1 200 5.5 5.5
Approx. Price (US$) 0.25 | 1ku 0.42 | 1ku 1.00 | 1ku 1.50 | 1ku 0.77 | 1ku 0.46 | 1ku 0.46 | 1ku 3.42 | 1ku 3.42 | 1ku
CMRR(Min)(dB) 65 65 60 66 72 72
Iq per channel(Typ)(mA) 0.55 0.55 1 5.2 0.815 0.815
Offset Drift(Typ)(uV/C) 2 2 2 4.5 1 1
Rating Catalog Catalog HiRel Enhanced Product Catalog Catalog Catalog Catalog Catalog Catalog Catalog
Vn at 1kHz(Typ)(nV/rtHz) 39 39 17 7.5 8 8
Total Supply Voltage(Max)(+5V=5, +/-5V=10) 16 16 5.5 5.5 5.5
Package Size mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2
Vos (Offset Voltage @ 25C)(Max)(mV) 5 5 1.6 6.5 6.5 10 0.100 0.100
Input Bias Current(Max)(pA) 60 60 3
Architecture CMOS CMOS CMOS CMOS CMOS CMOS
Total Supply Voltage(Min)(+5V=5, +/-5V=10) 2.7 2.7 2.5 2.2 2.2
Slew Rate(Typ)(V/us) 2.1 2.1 10.5 150 2 2
Number of Channels(#) 1 4 2 1 2 2 1 1
Iq per channel(Max)(mA) 0.66 0.66 2 5 5 6.5 1.2 1.2
Additional Features N/A N/A Cost Optimized,EMI Hardened Cost Optimized Cost Optimized
Output Current(Typ)(mA) 7 7 40 100 30 30
CMRR(Typ)(dB) 80 80 96 80 88 88
Operating Temperature Range(C) -40 to 125,0 to 70 -40 to 125,0 to 70 -55 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 85,0 to 70 -40 to 85,0 to 70
Package Group PDIP,SOIC,SOT-23 SOIC,TSSOP,PDIP SOIC SOIC,SOT-23 SOIC,SOT-23 SOIC,VSSOP SOIC,SOT-23 SOIC,SOT-23 PDIP,SOIC,VSSOP PDIP,SOIC,VSSOP
Rail-to-Rail In to V-,Out In to V-,Out In to V-,Out In,Out In,Out In,Out In,Out In,Out
IIB(Max)(pA) 60
Output Type Push-Pull Push-Pull Buffered Voltage Buffered Voltage
Input Bias Current (+/-)(Max)(nA) 0.01 0.01
Vs(Max)(V) 5.5 5.5
Special Features N/A N/A N/A N/A
VICR(Max)(V) 5.7 5.7
VICR(Min)(V) -0.2 -0.2
Vs(Min)(V) 2.7 2.7
tRESP Low - to - High(us) 0.0045 0.0045
Offset Error(Max)(%) N/A N/A
Code to Code Glitch(Typ)(nV-sec) 10 10
Interface SPI SPI
Settling Time(s) 3 3
Priority 1 1
Resolution(Bits) 12 12
Internal Reference Drift(Max)(ppm/degC) N/A N/A
Output Range Min.(mA/V) 0 0
DAC Architecture String String
Output Range Max.(mA/V) 5.1 5.1
Zero Code Error(Typ)(mV) 10 10
Gain Error(Max)(%FSR) 0.6 0.6
INL(Max)(+/-LSB) 4 4
Power Consumption(Typ)(mW) 0.9 0.9
Reference Type Type
Sample / Update Rate(MSPS) 0.102 0.102
DAC Channels Channels