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OPA2725AIDGKT

Texas Instruments OPA2725AIDGKT

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Texas Instruments P82B96PW

TPS79733DCKT

Texas Instruments TPS79733DCKT

INA155EA/250

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DAC6574IDGSR

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SN74AHCT126D

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LM385BD-2-5

Texas Instruments LM385BD-2-5

UCC27512DRST

Texas Instruments UCC27512DRST

Price $2.87 $0.83 $0.86 $0.46 $0.55
RoHS Yes Yes Yes Compliant Yes Yes Yes Compliant Yes Compliant
Lead Status Yes Yes Yes No Yes Yes Yes No Yes No
Iq per channel(Typ)(mA) 4.3 0.105
Total Supply Voltage(Max)(+5V=5, +/-5V=10) 12 16 16
CMRR(Min)(dB) 88 78 65 70
GBW(Typ)(MHz) 20 0.525 17
Vn at 1kHz(Typ)(nV/rtHz) 10 32 83
Rating Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog Catalog
Approx. Price (US$) 1.70 | 1ku 1.51 | 1ku 0.34 | 1ku 1.10 | 1ku 0.39 | 1ku 2.40 | 1ku 0.09 | 1ku 2.80 | 1ku 0.24 | 1ku 0.49 | 1ku
Iq per channel(Max)(mA) 5.5 0.28 60
Vos (Offset Voltage @ 25C)(Max)(mV) 3 10 20
Operating Temperature Range(C) -40 to 125 -40 to 85 -40 to 85 -40 to 85 0 to 70,-40 to 85 -40 to 105 -40 to 125,-40 to 85 -40 to 125 0 to 70 -40 to 140
Offset Drift(Typ)(uV/C) 4 1.7 50
CMRR(Typ)(dB) 94 91
Package Size mm2 mm2 mm2 mm2 mm2 mm2 mm2 mm2
Architecture CMOS CMOS
Number of Channels(#) 2 1 4 1 1
IIB(Max)(pA) 200 100
Package Group SOIC,VSSOP PDIP,SOIC,TSSOP,VSSOP SC70 SOIC,VSSOP PDIP,SO,SOIC,TSSOP VSSOP PDIP,SO,SOIC,SSOP,TSSOP,TVSOP HTSSOP SOIC,TO-92,TSSOP SON
Total Supply Voltage(Min)(+5V=5, +/-5V=10) 4 3 7
Additional Features N/A N/A
Output Current(Typ)(mA) 40 8
Input Bias Current(Max)(pA) 200 60
Rail-to-Rail In to V-,Out In to V-
Slew Rate(Typ)(V/us) 30 0.46 50
Channel Width 2
fSCLK(Max)(MHz) 0.4
Special Features Open-Drain I/O Type Power Good N/A Split Output
Master Side I2C Bus Capacitance Supported(pF) 400
No. of Outputs 2
VCC(Max)(V) 15 5.5
Max Frequency(kHz) 400
VCC(Min)(V) 2 4.5
Slave Side I2C Bus Capacitance Supported(pF) 4000
Iout(Max)(A) 0.05
Output Options Fixed Output
Vin(Max)(V) 5.5
Iq(Typ)(mA) 0.001 1.7
Regulated Outputs(#) 1
Vout(Max)(V) 3.3
Fixed Output Options(V) 1.8,2.85,3,3.3
Vout(Min)(V) 1.8
Accuracy(%) 4
Output Capacitor Type Ceramic
Vdo(Typ)(mV) 105
Vin(Min)(V) 1.8
Gain Non-Linearity (+/-)(Max)(%) 0.05
Input Bias Current (+/-)(Max)(nA) 0.05
Gain(Max)(V/V) 50
Gain(Min)(V/V) 10
Vs(Max)(V) 5.5 16
Gain Error (+/-)(Max)(%) 0.1
Vs(Min)(V) 2.7 7
Input Offset Drift (+/-)(Max)(uV/Degrees Celsius) 15
Bandwidth at Min Gain(Min)(MHz) 110
Bandwidth at Min Gain(Typ)(MHz) 0.55
Input Offset (+/-)(Max)(uV) 1000
Noise at 0.1 Hz - 10 Hz(Typ)(uVpp) 4.5
Gain(V/V) 10,50
Noise at 1kHz(Typ)(nV/rt(Hz)) 38
Settling Time(s) 9
Output Type Buffered Voltage CMOS
Sample / Update Rate(MSPS) 0.188
Output Range Max.(mA/V) 5.5
Offset Error(Max)(%) N/A
Resolution(Bits) 10
Priority 1
Internal Reference Drift(Max)(ppm/degC) N/A
Zero Code Error(Typ)(mV) 20
Output Range Min.(mA/V) 0
Code to Code Glitch(Typ)(nV-sec) 12
Gain Error(Max)(%FSR) 1
DAC Architecture String
DAC Channels
Interface I2C
INL(Max)(+/-LSB) 2
Reference Type
Power Consumption(Typ)(mW) 1.5
F @ Nom Voltage(Max)(Mhz) 110
tpd @ Nom Voltage(Max)(ns) 8.5
Schmitt Trigger No
ICC @ Nom Voltage(Max)(mA) 0.02
Voltage(Nom)(V) 5
Bits(#) 4
Technology Family AHCT
Input Type TTL
Output Drive (IOL/IOH)(Max)(mA) -8/8
Slew Rate(Min)(V/us) 50
Io(Typ)(mA) 1200
Estimated Package Size (WxL)(mm2) [pf]20HTSSOP[/pf]
VO Adj(Max)(V) 2.5
Reference Voltage Fixed
Pin/Package 3TO-92, 8SOIC, 8TSSOP
Min Iz for Regulation(uA) 8
Temp Coeff(Max)(ppm/ degree C) 20
VO(V) 2.5
VO Adj(Min)(V) 2.5
Iout/Iz(Max)(mA) 20
Initial Accuracy(Max)(%) 1.5
Temp Coeff(Typ)(ppm/ degree C) 20
Input Threshold CMOS,TTL
Prop Delay(ns) 13
Rise Time(ns) 9
Channel Input Logic Inverting,Non-Inverting
Input VCC(Max)(V) 18
Peak Output Current(A) 8
Power Switch MOSFET,IGBT,GaNFET
Input Negative Voltage(V) 0
Fall Time(ns) 7
Input VCC(Min)(V) 4.5