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TLV7022DSGR

Texas Instruments TLV7022DSGR

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Price
RoHS Y Y Y Y Y Y Y Y Y Y
Lead Status Y Y Y Y Y Y Y Y Y Y
Features Fail-safe,Hysteresis,POR Hysteresis,Small Size Fail-safe,Hysteresis,POR Fail-safe,Hysteresis,POR Fail-safe,Hysteresis,POR Enable,Output discharge Detection time delay,Manual reset capable,Reset time delay Detection time delay,Manual reset capable,Reset time delay Cost Optimized,EMI Hardened,Low Power,Shutdown,Small Size Cost Optimized,EMI Hardened,Low Power,Shutdown,Small Size
Input bias current ()(max)(nA) 0.002 0.002 0.002 0.002
Iq per channel(typ)(mA) 0.0047 0.00039 0.0003 0.0003 0.01 0.01
Number of channels 2 1 4 4 2 2
Operating temperature range(C) -40 -40 to 125 -40 -40 -40 -40 -40 -40 -40 -40
Output type Open-collector,Open-drain Push-pull Open-collector,Open-drain Open-collector,Open-drain Open-collector,Open-drain
Package area(mm^2) 4 4.2 32 9 1 8.12 8.12 4 19.2
Package size (L x W)(mm) 2 x 2 2 x 2.1 5 x 6.4 3 x 3 1 x 1 2.9 x 2.8 2.9 x 2.8 2 x 2 3 x 6.4
Package type WSON SOT-SC70 TSSOP WQFN X2SON SOT-23 SOT-23 WSON TSSOP
Pin count 8 5 14.0 16.0 4.0 5.0 5.0 8.0 8.0
Propagation delay time(s) 0.26 3 3 3 3
Rail-to-rail In In In In In In,Out In,Out
Rating Catalog Catalog Automotive Catalog Catalog Catalog Catalog Catalog Catalog Catalog
TI functional safety category
VICR(max)(V) 6.6 0 6.6 6.6
VICR(min)(V) 0 0 0 0
Vos (offset voltage at 25C)(max)(mV) 8 8 8 8 2.25 2.25
Vs(max)(V) 6.5 6.5 6.5 6.5
Vs(min)(V) 1.6 1.6 1.6 1.6
TI.com inventory 93185 5000 1510485 61800 104884 4675547 13955 98565 176222 141141
Approx. price(US$) .25 | 1ku .363 | 1ku .23 | 1ku .5 | 1ku .5 | 1ku .016 | 1ku .188 | 1ku .167 | 1ku .226 | 1ku .194 | 1ku
Vos (offset voltage @ 25 C)(Max)(mV) 8
Vs(Max)(V) 6.5
Input bias current (+/-)(Max)(nA) 0.002
Package Group SOT-23-THIN|8,VSSOP|8,WSON|8
Iq per channel(Max)(mA) 0.00075
Vs(Min)(V) 1.6
Iq per channel(Typ)(mA) 0.0003
Number of channels(#) 2
Package size mm2
VICR(Min)(V) 0
VICR(Max)(V) 6.6
Accuracy(%) 1
Dropout voltage (Vdo)(typ)(mV) 460
Fixed output options(V) 1.8
Iout(max)(A) 0.3
Iq(typ)(mA) 0.05 0.0001 0.0001
Load capacitance(min)(F) 1
Maximum package height(mm) 0.4
Noise(Vrms) 65
Output options Fixed Output
PSRR at 100 KHz(dB) 35
Regulated outputs(#) 1
Thermal resistance JA(C/W) 224
Vin(max)(V) 5.5
Vin(min)(V) 1.4
Vout(max)(V) 3.3
Vout(min)(V) 1
Number of supplies monitored 1 1
Output driver type/reset output Active-low,Open-drain Active-low,Open-drain
Reset threshold accuracy(%) 1 1
Supply voltage(max)(V) 6 6
Supply voltage(min)(V) 0.7 0.7
Threshold voltage 1(typ)(V) 1.3 3.3
Time delay(ms) 0.04 0.04
Watchdog timer WDI(s) None None
Architecture CMOS CMOS
CMRR(typ)(dB) 89 89
GBW(typ)(MHz) 0.35 0.35
Input bias current(max)(pA) 12 12
Input common mode headroom (to negative supply)(typ)(V) 0 0
Input common mode headroom (to positive supply)(typ)(V) 0 0
Iout(typ)(A) 0.04 0.04
Offset drift(typ)(V/C) 0.8 0.8
Output swing headroom (to negative supply)(typ)(V) 0.02 0.02
Output swing headroom (to positive supply)(typ)(V) 0.02 0.02
Slew rate(typ)(V/s) 0.2 0.2
TI package name DSG PW
Total supply voltage (+5 V = 5, 5 V = 10)(max)(V) 5.5 5.5
Total supply voltage (+5 V = 5, 5 V = 10)(min)(V) 1.2 1.2
Vn at 1 kHz(typ)(nVHz) 66 66