2.5V to 5.5V, 115A Parallel Interface Single Voltage Output 10-Bit DAC Features: Single 10-Bit DAC in 20-Lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Double-Buffered Input Logic Buffered/unbuffered reference input options See Data Sheet for Additional Information

2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 12-Bit DAC Features: AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL  B version: ±8 LSB INL 16-lead TSSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Micropower operation: 300 μA at 5 V (including reference current) 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Dual Low Power, High Speed JFET Operational Amplifier Features: Low supply current: 250 μA/amp maximum High slew rate: 9 V/μs Bandwidth: 3.5 MHz typical Low offset voltage: 1 mV maximum @ 25°C Low input bias current: 20 pA maximum @ 25°C CMRR: 90 dB typical Fast settling time Unity gain stable

Linear Voltage Regulator IC Positive Fixed 1 Output 150mA 8-MSOP

3000 V/S, 35mW Current Feedback Quad Amplifier Features: High speed 250 MHz -3 dB bandwidth (G = +1) 3000 V/µs slew rate 21 ns settling time to 0.1% 1.8 ns rise time for 2 V step Low power 3.5 mA/amp power supply Current (35 mW/amp) Single supply operation Fully specified for +5 V supply High output current of 50 mA Good video specifications (RL = 150 Ω, G = +2) Gain flatness 0.1 dB to 30 MHz 0.04% differential gain error 0.10° differential phase error Low distortion –78 dBc THD at 5 MHz –61 dBc THD at 20 MHz Available in a 14-lead SOIC

Single Supply, Low Power, Triple Video Amplifier Features: Three Video Amplifiers in One Package Drives Large Capacitive Load Excellent Video Specifications (RL = 150 ) Gain Flatness 0.1 dB to 60 MHz 0.02% Differential Gain Error 0.06° Differential Phase Error Low Power Operates on Single +5 V to +13 V Power Supplies 4 mA/Amplifier Max Power Supply Current High Speed 140 MHz Unity Gain Bandwidth (3 dB) Fast Settling Time of 18 ns (0.1%) 1000 V/µs Slew Rate High Speed Disable Function per Channel Turn-Off Time 30 ns Easy to Use 95 mA Short Circuit Current Output Swing to Within 1 V of Rails

160 MHz Rail-to-Rail Amplifier with Disable Features: Fully specified for +3 V, +5 V and ±5 V Supplies Output Swings Rail to Rail Input Voltage Range Extends 200 mV Below Ground No Phase Reversal with Inputs 1 V Beyond Supplies Disable/Power-Down Capability Low Power of 5.2 mA (26 mW on 5 V) High Speed and Fast Settling on 5 V: 160 MHz -3 dB Bandwidth (G = +2) 160 V/µs Slew Rate 30 ns Settling Time to 0.1% Good Video Specifications (RL = 150 Ω, G = +2) Gain Flatness of 0.1 dB to 30 MHz 0.03% Differential Gain Error 0.03° Differential Phase Error Low Distortion -69 dBc Worst Harmonic @ 10 MHz Outstanding Load Drive Capability Drives 50 mA 0.5 V from Supply Rails Cap Load Drive of 45 pF

Triple Differential Receiver with Adjustable Line Equalization Features: Compensates cables to 300 meters for wideband video Fast rise and fall times 4.9 ns with 2 V step at 150 meters of UTP cable 8.0 ns with 2 V step at 300 meters of UTP cable 55 dB peak gain at 100 MHz Two frequency response gain adjustment pins High frequency peaking adjustment (VPEAK) Broadband flat gain adjustment (VGAIN) Pole location adjustment pin (VPOLE) Compensates for variations between cables Can be optimized for either UTP or coaxial cable DC output offset adjust (VOFFSET) Low output offset voltage: 24 mV Compensates both RGB and YPbPr Two on-chip comparators with hysteresis Can be used for common-mode sync extraction Available in 40-lead, 6 mm × 6 mm LFCSP