Dual/Quad Rail-to-Rail Operational Amplifiers

5 V, 16 Mbps, ESD Protected, Full-Duplex RS-485 Transceiver Features: RS-485/RS-422 full-duplex transceiver for high speed motor control applications 16 Mbps data rate ±8 kV ESD protection on RS-485 input/output pins Open circuit fail-safe Suitable for 5 V power supply applications 32 nodes on the bus (1 unit load) See datasheet for additional features

Low Power, Wide Supply Range, Low Cost Unity-Gain Difference Amplifiers Features: Wide input range beyond supplies Rugged input overvoltage protection Low supply current: 200 μA maximum per channel Low power dissipation: 0.54 mW at VS = 2.7 V Bandwidth: 550 kHz CMRR: 86 dB minimum, dc to 10 kHz System offset voltage: ±2 μV/°C maximum (B Grade) Low gain drift: 1 ppm/°C maximum (B Grade) Enhanced slew rate: 1.1 V/μs Wide power supply range Single supply: 2.0 V to 36 V Dual supplies: ±2 V to ±18 V

TMP01 - Low Power Programmable Temperature Controller

ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, Word Access, CMOS, PDSO24

Low Capacitance, Low Charge Injection, 15 V/+12 V iCMOS Dual SPST Switches

1 Typical On Resistance, 5 V, +12 V, +5 V, and +3.3 V Quad SPST Switches Features: 1 Ω typical on resistance  0.2 Ω on resistance flatness  ±3.3 V to ±8 V dual-supply operation 3.3 V to 16 V single-supply operation No VL supply required  3 V logic-compatible inputs  Rail-to-rail operation See data sheet for additional features

Dual, 12-Bit, 80 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter Features: 1.8 V supply operation Low power: 115 mW per channel at 125 MSPS with scalable power options SNR = 71 dBFS (to Nyquist) SFDR = 93 dBc at 70 MHz DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Clock divider Programmable output clock and data alignment Programmable output resolution Standby mode

Quad 16-/14-/12-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface

Quad 14-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface Features: High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range