8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

Dual Low Power, High Speed JFET Operational Amplifier Features: Low supply current: 250 μA/amp maximum High slew rate: 9 V/μs Bandwidth: 3.5 MHz typical Low offset voltage: 1 mV maximum @ 25°C Low input bias current: 20 pA maximum @ 25°C CMRR: 90 dB typical Fast settling time Unity gain stable

Wideband VCO SMT w/Buffer Amplifier SMT, 6 - 12 GHz Features: Wide Tuning Bandwidth Pout: +1 dBm Low SSB Phase Noise: -95 dBc/Hz @100 kHz No External Resonator Needed Single Positive Supply: +5V @ 57 mA 24 Lead 4x4mm SMT Package: 16mm2

Wideband VCO SMT w/Buffer Amplifier SMT, 6 - 12 GHz Features: Wide Tuning Bandwidth Pout: +1 dBm Low SSB Phase Noise: -95 dBc/Hz @100 kHz No External Resonator Needed Single Positive Supply: +5V @ 57 mA 24 Lead 4x4mm SMT Package: 16mm2

VCO with Divide-by-4, 8.6 - 10.2 GHz Features: Dual Output: Fo = 8.6 - 10.2 GHz Fo/4 = 2.15 - 2.55 GHz Pout: +18 dBm Phase Noise: -100 dBc/Hz @ 100 kHz Typ. No External Resonator Needed 32 Lead 5×5 mm QFN Package: 25 mm2

Fractional-N PLL with Integrated VCO SMT, 1815 - 2010 MHz Features: RF Bandwidth: 1815 - 2010 MHz Fractional or Integer Modes 19-Bit Prescaler Ultra Low Phase Noise -110 dBc/Hz in Band Typ. Figure of Merit (FOM) -227 dBc Integer 24-Bit Step Size, 3 Hz Resolution Typ. 200 MHz, 14-bit Reference Path Input Cycle Slip Prevention 40 Lead 6x6mm SMT Package: 36mm²

11.90 GHz to 18.30 GHz Quadband VCO Features: Set of 4 narrow-band VCOs with consistent sensitivity vs. frequency RF and tuning ports common to all 4 VCOs RF output operates from fundamental oscillators with no subharmonic oscillations Up to 8 dBm RF output power Power mute capability No external resonator required 40-lead, 6 mm × 6 mm LFCSP

Fractional-N PLL with Integrated VCO SMT, 1.31 - 5.66 GHz Features: Ultra Low Phase Noise -112 dBc/Hz in Band Typ. Figure of Merit (FOM) -230 dBc Integer <180 fs RMS Jitter  24-Bit Step Size, 3 Hz Resolution Typ.  Exact Frequency Mode Built in Digital Self Test  40 Lead 6x6mm SMT Package: 36mm²

Low Noise Amplifier, 0.4 GHz to 11 GHz Features: Low noise figure: 1.4 dB typical Single positive supply (self biased) High gain: ≤15.5 dB typical High OIP3: ≤33 dBm typical RoHS-compliant, 2 mm × 2 mm, 6-lead LFCSPHMC8412TCPZ-EP Supports defense and aerospace applications (AQEC standard) Download the HMC8412TCPZ-EP data sheet (pdf) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/21602 DSCC Drawing Number

32 Gbps Limiting Amplifier SMT Features: Supports Data Rates up to 43 Gbps Low Power Dissipation: 300 mW @ VCC = +3.3V Differential Small Signal Gain: 30 dB High Input Sensitivity: 10 mVP-P Differential 3-dB Bandwidth: 26.5 GHz Adjustable Output Voltage Swing up to 800 mVP-P Differential 16 Lead 3x3mm SMT package: 9mm2