10-/12-/14-Bit, 1200 MSPS DACS Data Sheet  

SMD Data Sheet

2.7 V to 5.5 V, <100 A, 12-BitnanoDAC, SPI Interface in LFCSP and SC70 Features: 6-lead SC70 and LFCSP packages Micropower operation: 100 μA maximum at 5 V Power-down typically to 0.2 μA at 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility Minimized zero-code error AD5601 buffered 8-bit DAC B version: ±0.5 LSB INL AD5611 buffered 10-bit DAC B version: ±0.5 LSB INL A version: ±4 LSB INL AD5621 buffered 12-bit DAC B version: ±1 LSB INL A version: ±6 LSB INL

IC Operational Amplifier DUAL CMOS SOP 8PIN PLASTIC

ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, Word Access, CMOS, PDSO24

Low Capacitance, Low Charge Injection, 15 V/+12 V iCMOS Dual SPST Switches

DSP Microcomputer

High Performance, Digital Output Gyroscope

2 x 2 W, Filterless, Stereo, Class-D Audio Amplifier with ALC + I2C Features: Filterless, stereo, Class-D amplifier with Σ-Δ modulation 2 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) Highly configurable I2C interface for gain adjust, automatic level control (ALC), and ultralow EMI emissions mode MODE pin can disable I2C interface for more traditional stereo amplifier configuration Stereo-to-mono mixer option via I2C control 93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker Signal-to-noise ratio (SNR): >100 dB Single-supply operation from 2.5 V to 5.5 V Ultralow shutdown current: 20 nA Short-circuit and thermal protection Pop-and-click suppression Available in 16-ball, 2.0 mm × 2.0 mm WLCSP

Quad IF Receiver Features: 11-bit 200MSPS output data rate per channel Integrated Noise Shaping Requantizer (NSR) Performance with NSR enabled: SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS Performance with NSR disabled: SNR: 66.5 dBFS to 70 MHz @ 185 MSPS SFDR: 83 dBc to 70 MHz @ 185 MSPS Low power: 1.2 W @ 185 MSPS 1.8 V analog supply operation 1.8 V LVDS (ANSI-644 levels) output 1-to-8 integer clock divider Internal ADC voltage reference 1.75 V p-p analog input range (programmable to 2.0 V p-p) Differential analog inputs with 800 MHz bandwidth See data sheet for additional features