Ultralow Power Voltage Detector with Disable Input and Low Threshold Voltages Features: Ultralow power consumption with ICC = 92 nA (typical) Precision, low voltage monitoring Pretrimmed voltage monitoring threshold options 20 options from 0.5 V to 1.9 V ±1.3% threshold accuracy over full temperature range Output disable input 23 µs to 26 µs typical propagation delay Open-drain type output Power supply glitch immunity Available in a 1.46 mm × 0.96 mm WLCSP Operational temperature range: −40°C to +85°C

K Band Quadrature Demodulator with Integrated Fractional-N PLL and VCO Features: Fractional-N synthesizer with low phase noise VCO K band quadrature demodulator Programmable via 4-wire SPI RF operating frequency range: 17 GHz to 22 GHz LO internal frequency range: 17 GHz to 21.5 GHz Double sideband noise figure: 5 dB at maximum conversion gain Output integrated phase noise, 1 kHz to 10 MHz: <1° Maximum conversion gain of >50 dB Conversion gain control range of >50 dB IM3 of −54 dBc at −30 dBm composite input level, ΔfRF = 1 MHz 3 baseband, SPI-selectable LPFs with corner frequencies of: 125 MHz, 250 MHz, and 500 MHz on each baseband path

15.1 GHz to 32 GHz, Tunable Band-Pass Filter Features:Amplitude settling time: 200 ns typicalWideband rejection: 30 dBSingle chip implementation40-lead, 6 mm 6 mm, RoHS compliant LFCSP

2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter Features: Digitally tunable, multioctave, high-pass and low-pass tuning Independent 3 dB frequency control for up to 4 GHz of bandwidth Optimal wideband rejection: 35 dB Single chip replacement for discrete filter banks Compact 9 mm × 9 mm, 56-terminal LGA packageENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard Military temperature range of −55°C to +105°C Controlled manufacturing baseline One assembly and test site One fabrication site Production change notification Qualification data available on request V62/21604

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp Features: Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible (LVPECL/LVDS only at 155.52 MHz) Optional 19.44 MHz on-chip oscillator to be used with external crystal Loss-of-lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation: 3.3 V Low power: 540 mW typical 7 mm × 7 mm, 48-lead LFCSP

5.7 kV RMS/1.5 kV RMS, Quad-Channel LVDS 2.5 Gigabit Isolator (0 Reverse Channels) Features: 5.7 kV rms and 1.5 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS signal levels Quad-channel configuration Any data rate up to 2.5 Gbps switching with low jitter 10 Gbps total bandwidth across four channels 2.15 ns typical propagation delay Typical jitter: 0.82 ps rms random, 40 ps total peak Lower power 1.8 V supplies ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: 100 kV/μs typical Safety and regulatory approvals (28-lead SOIC_W_FP package) UL (pending): 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 VIORM = 849 VPEAK (working voltage) Enable or disable refresh (low speed output correctness check) Operating temperature range: −40°C to +125°C 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance or 6 mm × 6 mm LFCSP package with 1.27 mm creepage and clearance

5 kV RMS/3.75 kV RMS, Dual LVDS Gigabit Isolator (0 Reverse Channels) Features: 5 kV rms and 3.75 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Any data rate up to 1.1 Gbps switching with low jitter 4 ns typical propagation delay 2.6 ps rms typical random jitter, rms 90 ps typical peak-to-peak total jitter at 1.1 Gbps 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection, phase spur level Glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with 1.1 Gbps PRBS Safety and regulatory approvals (20-lead SOIC_W package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VPEAK Fail-safe output high for open, short, and terminated input conditions (ADN4655/ADN4656) Operating temperature range: −40°C to +125°C 7.8 mm minimum creepage and clearance

5 kV RMS/3.75 kV RMS, Dual LVDS Gigabit Isolator (Second Channel Reversed) Features: 5 kV rms and 3.75 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Any data rate up to 1.1 Gbps switching with low jitter 4 ns typical propagation delay 2.6 ps rms typical random jitter, rms 90 ps typical peak-to-peak total jitter at 1.1 Gbps 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection, phase spur level Glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with 1.1 Gbps PRBS Safety and regulatory approvals (20-lead SOIC_W package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VPEAK Fail-safe output high for open, short, and terminated input conditions (ADN4655/ADN4656) Operating temperature range: −40°C to +125°C 7.8 mm minimum creepage and clearance

Dual, 3 V, CMOS, LVDS High Speed Differential Driver Features:15 kV ESD protection on output pins600 Mbps (300 MHz) switching ratesFlow-through pinout simplifies PCB layout300 ps typical differential skew700 ps maximum differential skew1.5 ns maximum propagation delay3.3 V power supply355 mV differential signalingLow power dissipation: 23 mW typicalInteroperable with existing 5 V LVDS receiversConforms to TIA/EIA-644 LVDS standardIndustrial operating temperature range (40C to +85C)

250 Mbps, Half Duplex, Quad M-LVDS Transceivers Features: Four M-LVDS transceivers (driver and receiver pairs) Switching rate: 250 Mbps (125 MHz) Independent pin select for each receiver, two modes: Type 1: input hysteresis of 15 mV typical Type 2: differential input threshold voltage offset by 100 mV to support open-circuit, short-circuit, and bus idle fail-safe Compatible with the TIA/EIA-899 standard for M-LVDS Glitch free power-up/power-down on the M-LVDS bus Controlled transition times on the driver output Common-mode range: −1 V to +3.4 V, allowing communication with ±2 V of ground noise Driver outputs high-Z when disabled or powered off Independent enable pins for each driver and receiver Enhanced ESD protection on bus pins ≥±15 kV HBM, air discharge ≥±8 kV HBM, contact discharge ≥±10 kV IEC 61000-4-2, air discharge ≥±8 kV IEC 61000-4-2, contact discharge Enhanced ±8 kV HBM ESD protection for all pins, contact discharge Operating temperature range: −40°C to +105°C Available in 48-lead, 7 mm x 7 mm LFCSP