40W SPDT Failsafe Switch SMT, 0.1 - 2.1 GHz Features: High Input P0.1dB: +46 dBm Tx Low Insertion Loss: 0.4 dB High IIP3: +74 dBm Single Positive Control: 0/ +3V to 0/ +8V Failsafe Operation; Tx 'On' when Unpowered 2 × 2mm DFN SMT Package

1.6 Watt Power Amplifier SMT, 0.4 - 2.2 GHz Features: Output IP3: +49 dBm 20.5 dB Gain @ 400 MHz 7.5 dB Gain @ 2100 MHz 41% PAE @ +32.5 dBm Pout +26 dBm CDMA2000 Channel Power @ -45 dBc ACP

I/Q Receiver SMT, 21 - 25 GHz Features: Conversion Gain: 9 dB Image Rejection: 18 dB 2 LO to RF Isolation: 35 dB Noise Figure: 3.5 dB Input IP3: 2 dBm RoHS Compliant 5x5 mm SMT Package

0.5dB LSB GaAs MMIC 6-Bit Digital Serial Control Attenuator, DC - 4 GHz Features: 0.5 dB LSB Steps to 31.5 dB TTL/CMOS Compatible Serial Data Interface SPI Compatible Serial Output ±0.25 dB Typical Step Error Single +5V Supply 4x4 mm SMT Package

1.6 Watt Power Amplifier SMT, 0.4 - 2.2 GHz Features: Output IP3: +51 dBm 21.5 dB Gain @ 400 MHz 8 dB Gain @ 2100 MHz 45% PAE @ +32 dBm Pout +25 dBm CDMA2000 Channel Power@ -45 dBc ACP Single +5V Supply Integrated Power Control (VPD) QSOP16G SMT Package: 29.4 mm²

Phase-Locked Oscillator SMT, 14.7 - 15.4 GHz Features: Pout: +9 dBm Phase Noise: -110 dBc/Hz @100 KHz Typ. Single Supply: +5V @ 340 mA, 12V @ 28 mA QFN Leadless SMT Package, 16 mm2

2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 12-Bit DAC Features: AD5313: 2 buffered 10-bit DACs in 1 package A version: ±4 LSB INL B version: ±2 LSB INL AD5323: 2 buffered 12-bit DACs in 1 package A version: ±16 LSB INL  B version: ±8 LSB INL 16-lead TSSOP package Power-down to 200 nA @ 5 V, 50 nA @ 3 V Micropower operation: 300 μA at 5 V (including reference current) 2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to VREF or 0 V to 2 VREF Power-on-reset to 0 V

+2.5 V to 5.5 V, 400 A, Quad Rail-To-Rail Output 12-Bit DAC Features: Four 12-Bit DACS in 16-Lead TSSOP Low Power: 500 µA @ 5 V, 400 µA @ 3 V Power-Down to 300 nA @ 5 V, 90nA @ 3 V Guaranteed Monotonic by Design Power-On-Reset to Zero Volts Double-Buffered Input Logic Low Power, SPI™, QSPI™, MICROWIRE™ and DSP-Compatible 3-Wire Serial Interface Output Range: O-VREF or O-2VREF Simultaneous Update of DAC Outputs via LDAC pin (active low) Asynchronous Clear Facility via CLR pin (active low) SDO Daisy-Chaining Option Buffered/Unbuffered Reference Input Options for each DAC pair

Dual 10-Bit nanoDAC with 2 ppm/C Reference, I2C Interface Features: Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface See data sheet for additional features

2.5 V to 5.5 V, 250 A, 2-Wire Interface, Dual Voltage Output,12-Bit DACs Features: AD5337: 2 buffered 8-bit DACs in 8-lead MSOP AD5338, AD5338-1: 2 buffered 10-bit DACs in 8-lead MSOP AD5339: 2 buffered 12-bit DACs in 8-lead MSOP Low power operation: 250 μA @ 3 V, 300 μA @ 5 V 2-wire (I2C-compatible) serial interface 2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes See datasheet for additional features