|
|
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TLV3502AID
|
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TLV3542IDGKT
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TLV376IDBVR
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TLV376IDR
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TLV5616CDR
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TLV5616IDGKR
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TLV5619IPWR
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TLV5623CDR
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TLV5633CPW
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TLV5636IDG4
|
| Price |
|
$3.26 |
|
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| RoHS |
|
Compliant |
Compliant |
Compliant |
Compliant |
Yes |
Compliant |
Compliant |
Compliant |
Yes |
Compliant |
| Lead Status |
|
No |
No |
No |
No |
Yes |
No |
No |
No |
Yes |
No |
| Vos (Offset Voltage @ 25C)(Max)(mV) |
|
6.5 |
10 |
0.100 |
0.100 |
|
|
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|
|
|
| Output Type |
|
Push-Pull |
|
|
|
Buffered Voltage |
Buffered Voltage |
Buffered Voltage |
Buffered Voltage |
Buffered Voltage |
Buffered Voltage |
| Rating |
|
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
Catalog |
| Iq per channel(Max)(mA) |
|
5 |
6.5 |
1.2 |
1.2 |
|
|
|
|
|
|
| Input Bias Current (+/-)(Max)(nA) |
|
0.01 |
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| Operating Temperature Range(C) |
|
-40 to 125 |
-40 to 125 |
-40 to 125 |
-40 to 125 |
-40 to 85,0 to 70 |
-40 to 85,0 to 70 |
0 to 70,-40 to 85 |
-40 to 85,0 to 70 |
-40 to 85,0 to 70 |
-40 to 85,0 to 70 |
| Vs(Max)(V) |
|
5.5 |
|
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| Special Features |
|
N/A |
|
|
|
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
| VICR(Max)(V) |
|
5.7 |
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| VICR(Min)(V) |
|
-0.2 |
|
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| Package Group |
|
SOIC,SOT-23 |
SOIC,VSSOP |
SOIC,SOT-23 |
SOIC,SOT-23 |
PDIP,SOIC,VSSOP |
PDIP,SOIC,VSSOP |
SOIC,TSSOP |
SOIC,VSSOP |
TSSOP,SOIC |
SOIC,VSSOP |
| Vs(Min)(V) |
|
2.7 |
|
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|
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| Rail-to-Rail |
|
In,Out |
In,Out |
In,Out |
In,Out |
|
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| Number of Channels(#) |
|
2 |
2 |
1 |
1 |
|
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|
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| Package Size |
|
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
mm2 |
| tRESP Low - to - High(us) |
|
0.0045 |
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| Approx. Price (US$) |
|
1.50 | 1ku |
0.77 | 1ku |
0.46 | 1ku |
0.46 | 1ku |
3.42 | 1ku |
3.42 | 1ku |
5.04 | 1ku |
1.10 | 1ku |
5.58 | 1ku |
5.34 | 1ku |
| Output Current(Typ)(mA) |
|
|
100 |
30 |
30 |
|
|
|
|
|
|
| CMRR(Min)(dB) |
|
|
66 |
72 |
72 |
|
|
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|
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| Offset Drift(Typ)(uV/C) |
|
|
4.5 |
1 |
1 |
|
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| Vn at 1kHz(Typ)(nV/rtHz) |
|
|
7.5 |
8 |
8 |
|
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| Total Supply Voltage(Min)(+5V=5, +/-5V=10) |
|
|
2.5 |
2.2 |
2.2 |
|
|
|
|
|
|
| GBW(Typ)(MHz) |
|
|
200 |
5.5 |
5.5 |
|
|
|
|
|
|
| Iq per channel(Typ)(mA) |
|
|
5.2 |
0.815 |
0.815 |
|
|
|
|
|
|
| Input Bias Current(Max)(pA) |
|
|
3 |
|
|
|
|
|
|
|
|
| Architecture |
|
|
CMOS |
CMOS |
CMOS |
|
|
|
|
|
|
| Total Supply Voltage(Max)(+5V=5, +/-5V=10) |
|
|
5.5 |
5.5 |
5.5 |
|
|
|
|
|
|
| CMRR(Typ)(dB) |
|
|
80 |
88 |
88 |
|
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|
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| Slew Rate(Typ)(V/us) |
|
|
150 |
2 |
2 |
|
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|
|
|
|
| Additional Features |
|
|
Cost Optimized,EMI Hardened |
Cost Optimized |
Cost Optimized |
|
|
|
|
|
|
| Offset Error(Max)(%) |
|
|
|
|
|
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
| Code to Code Glitch(Typ)(nV-sec) |
|
|
|
|
|
10 |
10 |
5 |
10 |
5 |
5 |
| Interface |
|
|
|
|
|
SPI |
SPI |
Parallel |
SPI |
Parallel |
SPI |
| Settling Time(s) |
|
|
|
|
|
3 |
3 |
1 |
3 |
1 |
1 |
| Priority |
|
|
|
|
|
1 |
1 |
1 |
1 |
1 |
1 |
| Resolution(Bits) |
|
|
|
|
|
12 |
12 |
12 |
8 |
12 |
12 |
| Internal Reference Drift(Max)(ppm/degC) |
|
|
|
|
|
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
| Output Range Min.(mA/V) |
|
|
|
|
|
0 |
0 |
0 |
0 |
0 |
0 |
| DAC Architecture |
|
|
|
|
|
String |
String |
String |
String |
String |
String |
| Output Range Max.(mA/V) |
|
|
|
|
|
5.1 |
5.1 |
5.1 |
5.1 |
5.1 |
5.1 |
| Zero Code Error(Typ)(mV) |
|
|
|
|
|
10 |
10 |
20 |
10 |
20 |
20 |
| Gain Error(Max)(%FSR) |
|
|
|
|
|
0.6 |
0.6 |
0.5 |
0.6 |
0.3 |
0.6 |
| INL(Max)(+/-LSB) |
|
|
|
|
|
4 |
4 |
4 |
0.5 |
3 |
4 |
| Power Consumption(Typ)(mW) |
|
|
|
|
|
0.9 |
0.9 |
4.3 |
2.1 |
2.7 |
4.5 |
| Reference |
|
|
|
|
|
Type |
Type |
Type |
Type |
Type |
Type |
| Sample / Update Rate(MSPS) |
|
|
|
|
|
0.102 |
0.102 |
1 |
0.102 |
0.286 |
0.233 |
| DAC |
|
|
|
|
|
Channels |
Channels |
Channels |
Channels |
Channels |
Channels |
