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|
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INA206AIDG4
|
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TPS5431DDAG4
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LM5036RJBR
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LMV358AIDGKR
|
| Price |
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| RoHS |
|
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Y |
Compliant |
| Lead Status |
|
No |
No |
No |
No |
No |
No |
No |
No |
Y |
No |
| Topology |
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Full-Bridge,Half-Bridge,Push-Pull |
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| Rating |
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Catalog |
Catalog |
| Frequency(Max)(kHz) |
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2000 |
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| Package size |
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mm2 |
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| Control method |
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Feedforward,Voltage |
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| Features |
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Current Limiting,Frequency Synchronization,HV Start-up,Input Line Monitor,Integrated Switch,Leading Edge Blanking,Multi-topology,Pre-Bias Start-Up,Soft Start,Synchronization Pin,Thermal Shutdown,Wide DC input |
Cost Optimized,EMI Hardened |
| Package Group |
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WQFN|28 |
SOIC,VSSOP |
| UVLO thresholds on/off(V) |
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Programmable/1.25V |
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| Duty cycle(Max)(%) |
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50 |
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| Gate drive(Typ)(A) |
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2 |
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| Operating temperature range(C) |
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-40 to 125 |
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| Approx. price(US$) |
|
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1.848 | 1ku |
|
| GBW(Typ)(MHz) |
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1 |
| CMRR(Min)(dB) |
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63 |
| Vos (Offset Voltage @ 25C)(Max)(mV) |
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4 |
| Operating Temperature Range(C) |
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-40 to 125 |
| Vn at 1kHz(Typ)(nV/rtHz) |
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33 |
| Offset Drift(Typ)(uV/C) |
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1 |
| Package Size |
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mm2 |
| Iq per channel(Max)(mA) |
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0.15 |
| CMRR(Typ)(dB) |
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95 |
| Architecture |
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CMOS |
| Total Supply Voltage(Min)(+5V=5, +/-5V=10) |
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|
1.8 |
| Number of Channels(#) |
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2 |
| Total Supply Voltage(Max)(+5V=5, +/-5V=10) |
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5.5 |
| Approx. Price (US$) |
|
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0.23 | 1ku |
| Iq per channel(Typ)(mA) |
|
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0.08 |
| Slew Rate(Typ)(V/us) |
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1.7 |
| Output Current(Typ)(mA) |
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|
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|
40 |
| Rail-to-Rail |
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In to V-,Out |
