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TLV2460QDRQ1
|
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TL4050C25IDCKTG4
|
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TLK3114SCGPV
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TLE2081IDRG4
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TLC27L2MD
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TLV2373ID
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TLC2652M-8DG4
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TLC2652AIP
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TLV5619IDWR
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Price |
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$1.69 |
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RoHS |
|
Compliant |
Compliant |
No |
|
Yes |
Yes |
Yes |
Compliant |
Yes |
Yes |
Lead Status |
|
No |
|
No |
|
Yes |
Yes |
Yes |
No |
Yes |
Yes |
CMRR(Min)(dB) |
|
66 |
|
|
|
65 |
55 |
|
|
120 |
|
Vn at 1kHz(Typ)(nV/rtHz) |
|
11 |
|
|
|
68 |
39 |
|
|
23 |
|
Architecture |
|
Bipolar |
|
|
|
CMOS |
CMOS |
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CMOS |
|
Additional Features |
|
Shutdown |
|
|
|
Vos Adj Pin |
Shutdown |
|
|
Zero Drift |
|
IIB(Max)(pA) |
|
14000 |
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|
|
|
|
|
|
|
|
Iq per channel(Typ)(mA) |
|
0.55 |
|
|
|
0.01 |
0.55 |
|
|
1.5 |
|
Offset Drift(Typ)(uV/C) |
|
2 |
|
|
|
1.4 |
2 |
|
|
0.01 |
|
Approx. Price (US$) |
|
0.84 | 1ku |
|
57.75 | 1ku |
|
|
0.80 | 1ku |
|
0.75 | 1ku |
2.67 | 1ku |
5.04 | 1ku |
GBW(Typ)(MHz) |
|
6.4 |
|
|
|
0.085 |
3 |
|
|
1.9 |
|
Operating Temperature Range(C) |
|
-40 to 125 |
|
0 to 70 |
|
-55 to 125 |
-40 to 125 |
|
-40 to 85 |
-40 to 85 |
0 to 70,-40 to 85 |
Package Group |
|
TSSOP |
|
BGA |
|
SOIC |
PDIP,SOIC,VSSOP |
|
SC70,SOT-23 |
PDIP,SOIC |
SOIC,TSSOP |
Rating |
|
Automotive |
|
|
|
Military |
Catalog |
|
Catalog |
Catalog |
Catalog |
Vos (Offset Voltage @ 25C)(Max)(mV) |
|
2 |
|
|
|
10 |
4.5 |
|
12 |
0.001 |
|
Slew Rate(Typ)(V/us) |
|
1.6 |
|
|
|
0.03 |
2.4 |
|
|
2.8 |
|
Package Size |
|
mm2 |
|
|
|
mm2 |
mm2 |
|
mm2 |
mm2 |
mm2 |
Input Bias Current(Max)(pA) |
|
14000 |
|
|
|
60 |
60 |
|
|
60 |
|
Rail-to-Rail |
|
In,Out |
|
|
|
In to V- |
In,Out |
|
In |
In to V-,Out |
|
Total Supply Voltage(Min)(+5V=5, +/-5V=10) |
|
2.7 |
|
|
|
4 |
2.7 |
|
|
3.8 |
|
Output Current(Typ)(mA) |
|
60 |
|
|
|
1 |
7 |
|
|
3 |
|
Number of Channels(#) |
|
1 |
|
|
|
2 |
2 |
|
1 |
1 |
|
CMRR(Typ)(dB) |
|
80 |
|
|
|
94 |
72 |
|
|
140 |
|
Iq per channel(Max)(mA) |
|
0.65 |
|
|
|
0.017 |
0.66 |
|
0.005 |
2.4 |
|
Total Supply Voltage(Max)(+5V=5, +/-5V=10) |
|
6 |
|
|
|
16 |
16 |
|
|
16 |
|
Gbps per Serial Channel(Min) |
|
|
|
2.5 |
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|
|
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|
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Power Consumption(Nom)(mW) |
|
|
|
2325 |
|
|
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|
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|
|
Supply Voltage(V) |
|
|
|
1.2 |
|
|
|
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Signal Conditioning |
|
|
|
Yes |
|
|
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|
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Package Size(mm2=WxL) |
|
|
|
[pf]289BGA[/pf] |
|
|
|
|
|
|
|
Gbps per Serial Channel(Max) |
|
|
|
3.125 |
|
|
|
|
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Output Compatibility |
|
|
|
LVPECL |
|
|
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Input Compatibility |
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|
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SSTL,HSTL (XGMII) |
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Number of Serial Channels |
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4 |
|
|
|
|
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Parallel Bus Width |
|
|
|
8,10 |
|
|
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tRESP Low - to - High(us) |
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|
|
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6 |
|
|
Vs(Max)(V) |
|
|
|
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5.5 |
|
|
Vs(Min)(V) |
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|
|
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|
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1.8 |
|
|
Special Features |
|
|
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|
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|
|
With Voltage Reference |
|
N/A |
Input Bias Current (+/-)(Max)(nA) |
|
|
|
|
|
|
|
|
0.01 |
|
|
Output Type |
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Push-Pull |
|
Buffered Voltage |
VICR(Min)(V) |
|
|
|
|
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|
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-0.2 |
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|
VICR(Max)(V) |
|
|
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5.7 |
|
|
Offset Error(Max)(%) |
|
|
|
|
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N/A |
Sample / Update Rate(MSPS) |
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|
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|
1 |
Settling Time(s) |
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|
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|
1 |
Resolution(Bits) |
|
|
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|
|
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|
|
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12 |
Gain Error(Max)(%FSR) |
|
|
|
|
|
|
|
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0.5 |
Zero Code Error(Typ)(mV) |
|
|
|
|
|
|
|
|
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|
20 |
Output Range Min.(mA/V) |
|
|
|
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|
|
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0 |
DAC Channels |
|
|
|
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1 |
Output Range Max.(mA/V) |
|
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5.1 |
DAC Architecture |
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|
String |
Power Consumption(Typ)(mW) |
|
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4.3 |
Interface |
|
|
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Parallel |
Code to Code Glitch(Typ)(nV-sec) |
|
|
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5 |
INL(Max)(+/-LSB) |
|
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4 |
Reference |
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Type |