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Texas Instruments
TL3842DE4-8
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STMicroelectronics
TL084ACN
|
Infineon Technologies AG
TLE4906LHALA1
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Infineon Technologies AG
TLI4970D025T4XUMA1
|
Texas Instruments
TLV2444CPWG4
|
Texas Instruments
TLC272CPWG4
|
Texas Instruments
TLE2027IDG4
|
Texas Instruments
TLC27L2AIDG4
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Texas Instruments
TLC5628CDWG4
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AVX
TLCR476M010XTA
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Price |
|
|
$0.86 |
|
$4.57 |
|
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RoHS |
|
Compliant |
Compliant |
Compliant |
Yes |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Compliant |
Lead Status |
|
Yes |
No |
No |
Yes |
No |
No |
No |
No |
No |
No |
Duty Cycle(Max)(%) |
|
100 |
|
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|
|
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|
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Operating Temperature Range(C) |
|
0 to 70 |
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|
-40 to 125,0 to 70 |
-40 to 85,0 to 70 |
0 to 70 |
|
-40 to 85,0 to 70 |
|
Rating |
|
Catalog |
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Catalog |
Catalog |
Catalog |
|
Catalog |
|
Frequency(Min)(kHz) |
|
47 |
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Approx. Price (US$) |
|
0.26 | 1ku |
|
|
|
1.07 | 1ku |
0.41 | 1ku |
1.09 | 1ku |
|
2.95 | 1ku |
|
Vin(Max)(V) |
|
30 |
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Frequency(Max)(kHz) |
|
500 |
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Special Features |
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Adjustable Switching Frequency,Error Amplifier,Multi-topology |
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N/A |
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Topology |
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Boost,Flyback,Forward |
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Package Group |
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PDIP,SOIC |
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SOIC,TSSOP |
PDIP,SO,SOIC,TSSOP |
SOIC |
|
PDIP,SOIC |
|
Control Method |
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Current |
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Vin(Min)(V) |
|
17.5 |
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UVLO Thresholds On/Off(V) |
|
16/10 |
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Gate Drive(Typ)(A) |
|
0.2 |
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CMRR(Typ)(dB) |
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|
|
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75 |
80 |
131 |
|
|
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GBW(Typ)(MHz) |
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|
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1.81 |
0.32 |
13 |
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Slew Rate(Typ)(V/us) |
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1.4 |
3.6 |
2.8 |
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Output Current(Typ)(mA) |
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15 |
10 |
35 |
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Iq per channel(Max)(mA) |
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1.1 |
1.6 |
5.3 |
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Offset Drift(Typ)(uV/C) |
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2 |
1.8 |
0.4 |
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CMRR(Min)(dB) |
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70 |
65 |
100 |
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Total Supply Voltage(Max)(+5V=5, +/-5V=10) |
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|
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|
10 |
16 |
38 |
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Iq per channel(Typ)(mA) |
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|
|
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0.75 |
0.7 |
3.8 |
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Vos (Offset Voltage @ 25C)(Max)(mV) |
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2 |
10 |
0.1 |
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Number of Channels(#) |
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4 |
2 |
1 |
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Vn at 1kHz(Typ)(nV/rtHz) |
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16 |
25 |
2.5 |
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Input Bias Current(Max)(pA) |
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|
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60 |
60 |
90000 |
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Architecture |
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CMOS |
CMOS |
Bipolar |
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Total Supply Voltage(Min)(+5V=5, +/-5V=10) |
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|
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2.7 |
3 |
8 |
|
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Package Size |
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|
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mm2 |
mm2 |
mm2 |
|
mm2 |
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Additional Features |
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N/A |
N/A |
N/A |
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Rail-to-Rail |
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In to V-,Out |
In to V- |
Out |
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Offset Error(Max)(%) |
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N/A |
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Interface |
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SPI |
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Output Type |
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Buffered Voltage |
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INL(Max)(+/-LSB) |
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1 |
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Zero Code Error(Typ)(mV) |
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30 |
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Power Consumption(Typ)(mW) |
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15 |
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Output Range Min.(mA/V) |
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|
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0 |
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Code to Code Glitch(Typ)(nV-sec) |
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N/A |
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Sample / Update Rate(MSPS) |
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0.045 |
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DAC Architecture |
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String |
|
DAC Channels |
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8 |
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Resolution(Bits) |
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8 |
|
Gain Error(Max)(%FSR) |
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1.7 |
|
Reference |
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Type |
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Settling Time(s) |
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10 |
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Output Range Max.(mA/V) |
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5 |
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