TL7702ACDR

Texas Instruments TL7702ACDR

TLV342IDGKRG4

Texas Instruments TLV342IDGKRG4

TLC5602CDWR

Texas Instruments TLC5602CDWR

TLV2322IPWG4

Texas Instruments TLV2322IPWG4

TLC1543CFNR

Texas Instruments TLC1543CFNR

TL7702ACDRE4

Texas Instruments TL7702ACDRE4

TLC7701QPE4

Texas Instruments TLC7701QPE4

TLC2274AQDRQ1

Texas Instruments TLC2274AQDRQ1

TLV5637CDRG4

Texas Instruments TLV5637CDRG4

TLC549IPSG4

Texas Instruments TLC549IPSG4

Price $0.34 $0.21
RoHS Yes Compliant Yes Compliant Compliant Compliant Compliant Yes Compliant Compliant
Lead Status Yes Yes No No Yes No
VCC(Max)(V) 18 18
Reset Threshold Accuracy(%) 2 2
Rating Catalog Catalog Catalog Catalog Automotive Catalog
Threshold Voltage 1(Typ)(V) 2.53 2.53
Package Size mm2 mm2 mm2 mm2 mm2 mm2
Watchdog Timer WDI(sec) None None
Approx. Price (US$) 0.18 | 1ku 1.90 | 1ku 2.00 | 1ku 0.18 | 1ku 0.90 | 1ku 3.95 | 1ku
Iq(Typ)(uA) 1800 1800
Special Features Manual Reset Manual Reset N/A
Operating Temperature Range(C) -40 to 85,0 to 70 0 to 70 -40 to 125,0 to 70 -40 to 85,0 to 70 -40 to 125 -40 to 85,0 to 70
Time Delay(ms) Programmable Programmable
Package Group PDIP,SOIC SOIC PDIP,PLCC,SOIC,SSOP PDIP,SOIC SOIC,TSSOP SOIC
Output Driver Type / Reset Output Active-high,Active-low,Open-drain Active-high,Active-low,Open-drain
Monitored Voltage 1 (typ)(Nom)(V) Adjustable Adjustable
# of supplies monitored 1 1
VCC(Min)(V) 3.5 3.5
Power Consumption(Typ)(mW) 80 4 4.2
Sample / Update Rate(MSPS) 30 0.278
Architecture I-Steering SAR CMOS
Resolution(Bits) 8 10 10
Interface Parallel CMOS SPI SPI
DAC Channels Channels
Input Range(Min)(V) 0
# Input Channels 11
INL(Max)(+/-LSB) 1 1
Digital Supply(Min)(V) 4.5
Sample Rate (max)(SPS) 38kSPS
Multi-Channel Configuration Multiplexed
Analog Voltage AVDD(Max)(V) 5.5
Input Type Single-Ended
Analog Voltage AVDD(Min)(V) 4.5
Digital Supply(Max)(V) 5.5
Input Range(Max)(V) 5.5
Reference Mode Ext
Integrated Features Oscillator
Output Current(Typ)(mA) 2.2
CMRR(Typ)(dB) 75
Additional Features High Cload Drive
Vos (Offset Voltage @ 25C)(Max)(mV) 0.95
Offset Drift(Typ)(uV/C) 2
CMRR(Min)(dB) 70
Total Supply Voltage(Max)(+5V=5, +/-5V=10) 16
Slew Rate(Typ)(V/us) 3.6
Number of Channels(#) 4
Iq per channel(Max)(mA) 1.5
Input Bias Current(Max)(pA) 60
GBW(Typ)(MHz) 2.18
Vn at 1kHz(Typ)(nV/rtHz) 9
Total Supply Voltage(Min)(+5V=5, +/-5V=10) 4.4
Iq per channel(Typ)(mA) 1.1
Rail-to-Rail In to V-,Out
Output Type Buffered Voltage
Offset Error(Max)(%) N/A
Priority 1
Internal Reference Drift(Max)(ppm/degC) N/A
Output Range Min.(mA/V) 0
DAC Architecture String
Output Range Max.(mA/V) 5.1
Reference Type
Settling Time(s) 0.8
Gain Error(Max)(%FSR) 0.6
Zero Code Error(Typ)(mV) 24
Code to Code Glitch(Typ)(nV-sec) 5